About: SoC circuits reliability and availability improvement

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Projekt, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	http://linked.opendata.cz/ontology/domain/vavai/Projekt
rdfs:seeAlso	http://www.isvav.cz/projectDetail.do?rowId=GA102/09/1668
Description	The project deals with the basic research in the area of digital systems architectures which will allow to increase their reliablity parameters. The objective is to develop a methodology which will allow to increase safety and tolerance against failures in SoC circuits. It will be possible to test these circuits by means of additionally configured IP cores which will allow to reduce hardware components needed for maintenance purposes and use dynamic self reconfiguration to repair them. These approaches combine redundancy and self-repair on different levels of reconfigurable blocks granularity. The reconfigurtion mechnisms will be investigated on various platforms utilising different levels of granularity. These activities will result in the methodology for the design of highly reliable systems with predefined fault tolerance and prediction of safe operation characteristics. The research will be performed on three universities which have sufficient experience with project management, they cooperate with both Czech and foreign institutions. (en) - Navrhnout metodiku testování obvodu SoC pomocí dodatečně nakonfigurovaných testovacích jader - Navrhnout nové architektury SoC systému odolného vůči poruchám - Navrhnout způsob rekonfigurace a granularitu rekonfigurovatelných bloků optimalizující provozuschopnost, spolehlivost a bezpečnost.
Title	SoC circuits reliability and availability improvement (en) Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC
skos:notation	GA102/09/1668
http://linked.open...avai/cep/aktivita	Standard projects
http://linked.open...kovaStatniPodpora	http://linked.opendata.cz/resource/domain/vavai/projekt/GA102%2F09%2F1668/celkovaStatniPodpora
http://linked.open...ep/celkoveNaklady	http://linked.opendata.cz/resource/domain/vavai/projekt/GA102%2F09%2F1668/celkoveNaklady
http://linked.open...datumDodatniDoRIV	2015-03-02 (xsd:date)
http://linked.open...i/cep/druhSouteze	VS - Veřejná soutěž ve výzkumu a vývoji
http://linked.open...ep/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open.../cep/fazeProjektu	91483587
http://linked.open...ai/cep/hlavniObor	JC - Počítačový hardware a software
http://linked.open...hodnoceniProjektu	U - Uspěl podle zadání, tj. byly splněny cíle a jeho předpokládané výsledky uvedené ve smlouvě / rozhodnutí o poskytnutí podpory
http://linked.open...vai/cep/kategorie	ZV - Základní výzkum
http://linked.open.../cep/klicovaSlova	návrh systémů odolných proti poruchám, dynamická rekonfigurace, diagnostika a testování, SoC (en)
http://linked.open...ep/partnetrHlavni	Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...inujicichPrijemcu	0 (xsd:int)
http://linked.open...cep/pocetPrijemcu	1 (xsd:int)
http://linked.open...ocetSpoluPrijemcu	2 (xsd:int)
http://linked.open.../pocetVysledkuRIV	88 (xsd:int)
http://linked.open...enychVysledkuVRIV	88 (xsd:int)
http://linked.open...lneniVMinulemRoce	2011-04-16 (xsd:date)
http://linked.open.../prideleniPodpory	http://linked.opendata.cz/resource/domain/vavai/cep/prideleniPodpory/102%2F09%2F1668
http://linked.open...iciPoslednihoRoku	2011
http://linked.open...atUdajeProjZameru	2012
http://linked.open.../vavai/cep/soutez	SGA02009GA-ST
http://linked.open...usZobrazovaneFaze	DUU
http://linked.open...ai/cep/typPojektu	P - Projekt výzkumu a vývoje financovaný ze státního rozpočtu
http://linked.open...ep/ukonceniReseni	2011-12-31 (xsd:date)
http://linked.open...ep/zahajeniReseni	2009-01-01 (xsd:date)
http://linked.open...jektu+dodavatelem	The project gone according to plan both in terms of expertise and in terms of disbursement of funds. (en) Řešení projektu proběhlo podle plánu jak z hlediska odborného tak i z hlediska čerpání finančních prostředků. (cs)
http://linked.open...tniCyklusProjektu	ZBKU
http://linked.open.../cep/klicoveSlovo	diagnostika a testování dynamická rekonfigurace návrh systémů odolných proti poruchám
is http://linked.open...vavai/riv/projekt of	The Observed Role of Structure in Logic Synthesis Examples TT-Min Experiments with Physical Error Injection into FPGA Circuits Fault-tolerant and fail-safe design based on reconfiguration Fault Models Usability Study for On-line Tested FPGA Increasing Dependability by Fitting Circuit on FPGA On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits On Test Compression Based on Pattern Overlapping and Broadcasting Scan Chain Configuration Method for Broadcast Decompressor Architecture Self Repair Architectures Based on Partial Dynamic and Static Reconfiguration Using Decomposition to Create Fault Secure Counters of the Railway Station Safety Device Techniques for SAT-Based Constrained Test Pattern Generation COMPAS III - compressed test pattern sequencer Application Dependent FPGA Testing Method Application dependent FPGA testing method using compressed deterministic test vectors Autíčko s modrým zubem Test Pattern Decompression in Parallel Scan Chain Architecture Simulátor elektronického stavědla s JOP Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads Decreasing Test Time by Scan Chain Reorganization Tool for scan chain routability visualisation, analysis and optimization It Is Better to Run Iterative Resynthesis on Parts of the Circuit Structural Test of Programmed FPGA Circuits SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems SEU Experiments Using Real FPGAs Test vector overlapping based compression tool for narrow test access mechanism Techniques for SAT-Based Constrained Test Pattern Generation Test pattern compression based on pattern overlapping and broadcasting Test Pattern Compression Based on Pattern Overlapping and Broadcasting Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA Advanced Scan Chain Configuration Method for Broadcast Decompressor Architecture Fault Classifier High Availability Fault Tolerant Architectures Implemented into FPGAs Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems Metodologie návrhu obvodů se zvýšenou spolehlivostí založených na FPGA The Design of On-line Checkers and Their Use in Verification and Testing Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel Methodology for Design of Highly Dependable Systems in FPGA Metodika pro návrh číslicových systémů se zvýšenou spolehlivostí v obvodech FPGA Gracefully Degrading Circuit Controllers Based on Polytronics Optimalizace propojení řetězce scan po ukončení fyzického návrhu The Use of Genetic Algorithm to Reduce Power Consumption during Test Application The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA Návrh časově kritických systémů I: specifikace a verifikace Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes On Properties of SAT Instances Produced by SAT-Based ATPGs Reconfiguration Strategy for FPGA Dependability Characteristics Improvement based on Stochastic Petri Net Reliable Railway Station System based on Regular Structure implemented in FPGA Single Event Upset Tolerant FPGA Design New design methodolgy for SRAM-based FPGAs using reconfiguration resources Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints Faults Coverage Improvement based on Fault Simulation and Partial Duplication Model of Modular Secured Designs for Calculations of Availability Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG Dependable Interconnection of Dependable Blocks

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