About: Reliable Railway Station System based on Regular Structure implemented in FPGA

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are %22Moore%22 type. Each state machine is divided into three basic parts, where each part is designed as a self-checking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed. The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are %22Moore%22 type. Each state machine is divided into three basic parts, where each part is designed as a self-checking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed. (en)
Title	Reliable Railway Station System based on Regular Structure implemented in FPGA Reliable Railway Station System based on Regular Structure implemented in FPGA (en)
skos:prefLabel	Reliable Railway Station System based on Regular Structure implemented in FPGA Reliable Railway Station System based on Regular Structure implemented in FPGA (en)
skos:notation	RIV/68407700:21240/09:00159471!RIV10-MSM-21240___
http://linked.open...avai/riv/aktivita	P Z
http://linked.open...avai/riv/aktivity	P(FI-IM4/149), P(GA102/09/1668), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat	2010
http://linked.open...aciTvurceVysledku	Kubátová, Hana Kubalík, Pavel
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	338858
http://linked.open...ai/riv/idVysledku	RIV/68407700:21240/09:00159471
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Fault Tolerant; FPGA; Finite State Machine; SEU; Secure Device; Railway Station (en)
http://linked.open.../riv/klicoveSlovo	SEU FPGA Fault Tolerant Secure Device Railway Station Finite State Machine
http://linked.open...ontrolniKodProRIV	[1E362E8F4910]
http://linked.open...v/mistoKonaniAkce	Patras
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	Proc. of 12th EUROMICRO Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement *Research and Development of High-rate Microwave Line Featured by QAM Modulation and the Transmission Speed of 155 Mbit/s.
http://linked.open...UplatneniVysledku	2009
http://linked.open...iv/tvurceVysledku	Kubátová, Hana Borecký, Jaroslav Kubalík, Pavel
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2009-08-27 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum perspektivních informačních a komunikačních technologií
number of pages	7 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-0-7695-3782-5
http://localhost/t...ganizacniJednotka	21240
is http://linked.open...avai/riv/vysledek of	Reliable Railway Station System based on Regular Structure implemented in FPGA Reliable Railway Station System based on Regular Structure implemented in FPGA Reliable Railway Station System based on Regular Structure implemented in FPGA Reliable Railway Station System based on Regular Structure implemented in FPGA

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