About: Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, concept and early analysis of an embedded HW/SW architecture designed to prevent the SW from interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt to various interrupt rates according to the actual MCU load. The adaptation is possible because the HW is both informed about the actual SW load on basis of signals send from the SW to the HW and able to buffer all interrupts incomming to the MCU when the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded. In the paper, concept and early analysis of an embedded HW/SW architecture designed to prevent the SW from interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the HW (SW) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt to various interrupt rates according to the actual MCU load. The adaptation is possible because the HW is both informed about the actual SW load on basis of signals send from the SW to the HW and able to buffer all interrupts incomming to the MCU when the SW is highly loaded or redirect the interrupts to the MCU as soon as the SW becomes underloaded. (en)
Title	Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads (en)
skos:prefLabel	Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads (en)
skos:notation	RIV/00216305:26230/11:PU96073!RIV12-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(7H10013), P(GA102/09/1668), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2012
http://linked.open...aciTvurceVysledku	Strnadel, Josef
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	191588
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/11:PU96073
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	FPGA, MCU, interrupt, rate, limit, overload, burst, utilization, load, adaptation (en)
http://linked.open.../riv/klicoveSlovo	FPGA MCU adaptation burst interrupt limit load overload rate utilization
http://linked.open...ontrolniKodProRIV	[8DE0D7FE01A3]
http://linked.open...v/mistoKonaniAkce	Oulu
http://linked.open...i/riv/mistoVydani	Oulu
http://linked.open...i/riv/nazevZdroje	Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	1 (xsd:int)
http://linked.open...vavai/riv/projekt	Reduced Certification Costs for Trusted Multi-core Platforms SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Strnadel, Josef
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-08-31 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	2 (xsd:int)
http://purl.org/ne...btex#hasPublisher	Johannes Kepler University Linz
https://schema.org/isbn	978-3-902457-30-1
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads

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