About: SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology. In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology. (en)
Title	SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems (en)
skos:prefLabel	SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems (en)
skos:notation	RIV/00216305:26230/11:PU96032!RIV13-MSM-26230___
http://linked.open...avai/predkladatel	Fakulta informačních technologií
http://linked.open...avai/riv/aktivita	P S Z
http://linked.open...avai/riv/aktivity	P(GA102/09/1668), S, Z(MSM0021630528)
http://linked.open...vai/riv/dodaniDat	2013
http://linked.open...aciTvurceVysledku	Straka, Martin Kotásek, Zdeněk Kaštil, Jan
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Vysoké učení technické v Brně / Fakulta informačních technologií
http://linked.open...dnocenehoVysledku	229030
http://linked.open...ai/riv/idVysledku	RIV/00216305:26230/11:PU96032
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	SEU, simulatotion, generator, framework, online testing, fault tolerance (en)
http://linked.open.../riv/klicoveSlovo	SEU fault tolerance framework online testing simulatotion generator
http://linked.open...ontrolniKodProRIV	[E17B8A69CFAA]
http://linked.open...v/mistoKonaniAkce	Oulu
http://linked.open...i/riv/mistoVydani	Oulu
http://linked.open...i/riv/nazevZdroje	14th EUROMICRO Conference on Digital System Design
http://linked.open...in/vavai/riv/obor	IN
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	SoC circuits reliability and availability improvement
http://linked.open...UplatneniVysledku	2011
http://linked.open...iv/tvurceVysledku	Kaštil, Jan Kotásek, Zdeněk Straka, Martin
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2011-08-31 (xsd:date)
http://linked.open...n/vavai/riv/zamer	Výzkum informačních technologií z hlediska bezpečnosti
number of pages	8 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-0-7695-4494-6
http://localhost/t...ganizacniJednotka	26230
is http://linked.open...avai/riv/vysledek of	SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems

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