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Description
  • The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are ?Moore? type. Each state machine is divided into three basic parts, where each part is designed as a selfchecking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.
  • The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are ?Moore? type. Each state machine is divided into three basic parts, where each part is designed as a selfchecking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed. (en)
Title
  • Design of scalable structures with defined dependability for system on chip
  • Design of scalable structures with defined dependability for system on chip (en)
skos:prefLabel
  • Design of scalable structures with defined dependability for system on chip
  • Design of scalable structures with defined dependability for system on chip (en)
skos:notation
  • RIV/68407700:21230/10:00166068!RIV15-MSM-21230___
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/09/1668), S, Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 253554
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/10:00166068
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • FPGA; SEU; FSM; Fault tolerant (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [6A5469C36393]
http://linked.open...v/mistoKonaniAkce
  • Praha
http://linked.open...i/riv/mistoVydani
  • Praha
http://linked.open...i/riv/nazevZdroje
  • Workshop 2010
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Borecký, Jaroslav
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • České vysoké učení technické v Praze
https://schema.org/isbn
  • 978-80-01-04513-8
http://localhost/t...ganizacniJednotka
  • 21230
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