About: Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
Description	This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses built-in processor for test control and the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams. (en) Elánek popisuje metodologi ivytvooení vestaviného diagnostického systému do Soc obvodu. (cs)
Title	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Samoeinné testování SoC obvodu s redukovanou potoebou pameti a minimalizovaným hardwarovym po3adavkem (cs) Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead (en)
skos:prefLabel	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Samoeinné testování SoC obvodu s redukovanou potoebou pameti a minimalizovaným hardwarovym po3adavkem (cs) Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead (en)
skos:notation	RIV/68407700:21230/06:03121303!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany	300 ; 308
http://linked.open...avai/riv/aktivita	P
http://linked.open...avai/riv/aktivity	P(1QS108040510), P(GA102/04/2137)
http://linked.open...vai/riv/dodaniDat	2007
http://linked.open...aciTvurceVysledku	Novák, Ondřej
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	České vysoké učení technické v Praze / Fakulta elektrotechnická
http://linked.open...dnocenehoVysledku	498808
http://linked.open...ai/riv/idVysledku	RIV/68407700:21230/06:03121303
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Not available (en)
http://linked.open.../riv/klicoveSlovo	Not available
http://linked.open...ontrolniKodProRIV	[CA0C87BF52EC]
http://linked.open...v/mistoKonaniAkce	Arlington
http://linked.open...i/riv/mistoVydani	Los Alamitos
http://linked.open...i/riv/nazevZdroje	The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	1 (xsd:int)
http://linked.open...cetTvurcuVysledku	5 (xsd:int)
http://linked.open...vavai/riv/projekt	Technology for improving the testability of modern digital circuits Design of highly reliable control systems built on dynamically reconfigurable FPGAs.
http://linked.open...UplatneniVysledku	2006
http://linked.open...iv/tvurceVysledku	Novák, Ondřej Mader, Z. Plíva, Z. Jarkovský, M. Jeníeek, J.
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2006-10-04 (xsd:date)
number of pages	9 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	0-7695-2706-X
http://localhost/t...ganizacniJednotka	21230
is http://linked.open...avai/riv/vysledek of	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

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