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Description
  • This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments.
  • This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments. (en)
  • Tento článek popisuje metodu emulace, která zachovává strukturu a případně i časování emulovaného obvodu podle cílové technologie. Tato emulační metoda umožňuje použít metody vkládání poruch založené jak na modifikaci obvodu, tak na dynamické rekonfiguraci. Článek dále obsahuje výsledky několika experientů týkajících se této metody. (cs)
Title
  • A Novel Emulation Technique that Preserves Circuit Structure and Timing
  • Nová emulační metoda, která zachovává strukturu a časování obvodu (cs)
  • A Novel Emulation Technique that Preserves Circuit Structure and Timing (en)
skos:prefLabel
  • A Novel Emulation Technique that Preserves Circuit Structure and Timing
  • Nová emulační metoda, která zachovává strukturu a časování obvodu (cs)
  • A Novel Emulation Technique that Preserves Circuit Structure and Timing (en)
skos:notation
  • RIV/67985556:_____/07:00090440!RIV08-AV0-67985556
http://linked.open.../vavai/riv/strany
  • 15;18
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(1QS108040510), Z(AV0Z10750506)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 408066
http://linked.open...ai/riv/idVysledku
  • RIV/67985556:_____/07:00090440
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • Fault emulation; FPGA; ASIC (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [D99B9EE433D0]
http://linked.open...v/mistoKonaniAkce
  • Tampere
http://linked.open...i/riv/mistoVydani
  • Tampere
http://linked.open...i/riv/nazevZdroje
  • International Symposium on System-on-Chip 2007 Proceedings
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Daněk, Martin
  • Kafka, Leoš
  • Novák, O.
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • IEEE
https://schema.org/isbn
  • 1-4244-1367-2
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