About: On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

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rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6841917&queryText%3DOn+reliability+enhancement+using+adaptive+core+voltage+scaling+and+variations+on+nanoscale+FPGAs
Description	Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems. Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems. (en)
Title	On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs (en)
skos:prefLabel	On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs (en)
skos:notation	RIV/46747885:24220/14:#0003129!RIV15-MSM-24220___
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(LD13019), S
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Plíva, Zdeněk Pfeifer, Petr
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	34359
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/14:#0003129
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Nanoscale device (en)
http://linked.open.../riv/klicoveSlovo	Nanoscale device
http://linked.open...ontrolniKodProRIV	[4E0F0AC5BAAE]
http://linked.open...v/mistoKonaniAkce	Fortaleza
http://linked.open...i/riv/mistoVydani	Brazil
http://linked.open...i/riv/nazevZdroje	15th IEEE Latin-American Test Workshop
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	2 (xsd:int)
http://linked.open...cetTvurcuVysledku	4 (xsd:int)
http://linked.open...vavai/riv/projekt	Improvement in Reliability of Nano-scale circuits
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Plíva, Zdeněk Pfeifer, Petr
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2014-01-01 (xsd:date)
number of pages	4 (xsd:int)
http://bibframe.org/vocab/doi	10.1109/LATW.2014.6841917
http://purl.org/ne...btex#hasPublisher	IEEE Computer Society
https://schema.org/isbn	978-1-4799-4711-9
http://localhost/t...ganizacniJednotka	24220

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