About: Test-Data Compression with Low Number of Channels and Short Test Time

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An Entity of Type : http://linked.opendata.cz/ontology/domain/vavai/Vysledek, within Data Space : linked.opendata.cz associated with source document(s)

Attributes	Values
rdf:type	skos:Concept http://linked.opendata.cz/ontology/domain/vavai/Vysledek
rdfs:seeAlso	http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=3&SID=R2Ihc8Vb4DCzHkD6jzl&page=1&doc=1
Description	The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompression that is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a way that the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results of benchmark circuit testing show that the modified Smart BIST methodology provides unreduced test coverage, low hardware overhead and short test sequences. The paper describes a modified Smart BIST methodology that provides test data volume compression. The test equipment is easily applicable because it is based on the standard scan methodology. The method is based on continuous LFSR reseeding decompression that is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. The parameters can be tuned in such a way that the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results of benchmark circuit testing show that the modified Smart BIST methodology provides unreduced test coverage, low hardware overhead and short test sequences. (en)
Title	Test-Data Compression with Low Number of Channels and Short Test Time Test-Data Compression with Low Number of Channels and Short Test Time (en)
skos:prefLabel	Test-Data Compression with Low Number of Channels and Short Test Time Test-Data Compression with Low Number of Channels and Short Test Time (en)
skos:notation	RIV/46747885:24220/14:#0003128!RIV15-MSM-24220___
http://linked.open...avai/riv/aktivita	P S
http://linked.open...avai/riv/aktivity	P(LD13019), S
http://linked.open...vai/riv/dodaniDat	2015
http://linked.open...aciTvurceVysledku	Rozkovec, Martin Jeníček, J. Novák, Ondřej
http://linked.open.../riv/druhVysledku	D - Článek ve sborníku
http://linked.open...iv/duvernostUdaju	S - Úplné a pravdivé údaje nepodléhající ochraně podle zvláštních právních předpisů
http://linked.open...titaPredkladatele	Technická univerzita v Liberci / Fakulta mechatroniky, informatiky a mezioborových studií
http://linked.open...dnocenehoVysledku	50037
http://linked.open...ai/riv/idVysledku	RIV/46747885:24220/14:#0003128
http://linked.open...riv/jazykVysledku	eng - angličtina
http://linked.open.../riv/klicovaSlova	Design for testability (en)
http://linked.open.../riv/klicoveSlovo	Design for testability
http://linked.open...ontrolniKodProRIV	[54240B7D22B4]
http://linked.open...v/mistoKonaniAkce	Warsaw, POLAND
http://linked.open...i/riv/mistoVydani	Warsaw, POLAND
http://linked.open...i/riv/nazevZdroje	PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS)
http://linked.open...in/vavai/riv/obor	JC
http://linked.open...ichTvurcuVysledku	3 (xsd:int)
http://linked.open...cetTvurcuVysledku	3 (xsd:int)
http://linked.open...vavai/riv/projekt	Improvement in Reliability of Nano-scale circuits
http://linked.open...UplatneniVysledku	2014
http://linked.open...iv/tvurceVysledku	Jeníček, Jiří Novák, Ondřej Rozkovec, Martin
http://linked.open...vavai/riv/typAkce	WRD - Světová
http://linked.open.../riv/zahajeniAkce	2014-01-01 (xsd:date)
issn	2334-3133
number of pages	6 (xsd:int)
http://purl.org/ne...btex#hasPublisher	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
https://schema.org/isbn	978-1-4799-4558-0
http://localhost/t...ganizacniJednotka	24220

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