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Description
  • Není k dispozici (cs)
  • This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against Single Even Upsets (SEUs). This adapted duplex system is realized by two FPGAs, where each FPGA can be reconfigured when a fault is detected. Availability parameters have been calculated by dependability Markov models.
  • This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against Single Even Upsets (SEUs). This adapted duplex system is realized by two FPGAs, where each FPGA can be reconfigured when a fault is detected. Availability parameters have been calculated by dependability Markov models. (en)
Title
  • Dependability Computation for Fault Tolerant Reconfigurable Duplex System
  • Není k dispozici (cs)
  • Dependability Computation for Fault Tolerant Reconfigurable Duplex System (en)
skos:prefLabel
  • Dependability Computation for Fault Tolerant Reconfigurable Duplex System
  • Není k dispozici (cs)
  • Dependability Computation for Fault Tolerant Reconfigurable Duplex System (en)
skos:notation
  • RIV/68407700:21230/06:03120122!RIV07-GA0-21230___
http://linked.open.../vavai/riv/strany
  • 100 ; 102
http://linked.open...avai/riv/aktivita
http://linked.open...avai/riv/aktivity
  • P(GA102/04/2137), Z(MSM6840770014)
http://linked.open...vai/riv/dodaniDat
http://linked.open...aciTvurceVysledku
http://linked.open.../riv/druhVysledku
http://linked.open...iv/duvernostUdaju
http://linked.open...titaPredkladatele
http://linked.open...dnocenehoVysledku
  • 470782
http://linked.open...ai/riv/idVysledku
  • RIV/68407700:21230/06:03120122
http://linked.open...riv/jazykVysledku
http://linked.open.../riv/klicovaSlova
  • dependability, fault-tolerant, reconfiguration, FPGA, duplex system (en)
http://linked.open.../riv/klicoveSlovo
http://linked.open...ontrolniKodProRIV
  • [4F9A74D2ADB8]
http://linked.open...v/mistoKonaniAkce
  • Praha
http://linked.open...i/riv/mistoVydani
  • Praha
http://linked.open...i/riv/nazevZdroje
  • Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
http://linked.open...in/vavai/riv/obor
http://linked.open...ichTvurcuVysledku
http://linked.open...cetTvurcuVysledku
http://linked.open...vavai/riv/projekt
http://linked.open...UplatneniVysledku
http://linked.open...iv/tvurceVysledku
  • Kubátová, Hana
  • Kubalík, Pavel
  • Dobiá1, Radek
http://linked.open...vavai/riv/typAkce
http://linked.open.../riv/zahajeniAkce
http://linked.open...n/vavai/riv/zamer
number of pages
http://purl.org/ne...btex#hasPublisher
  • Česká technika - nakladatelství ČVUT
https://schema.org/isbn
  • 1-4244-0184-4
http://localhost/t...ganizacniJednotka
  • 21230
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