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Statements

Subject Item
n2:RIV%2F26821532%3A_____%2F13%3A%230000034%21RIV13-TA0-26821532
rdf:type
n6:Vysledek skos:Concept
dcterms:description
We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the final chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydrofluoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0.8 um to the thickness target of the lightly doped epitaxial layer (future device layer) and using CMP stock removal of 0.2 um to obtain BESOI wafer with superior device layer surface micro-roughness and thickness uniformity. We have studied the bond and etch-back silicon on insulator (BESOI) manufacturing processes. The top silicon layer, called device layer, was studied from its epitaxial growth on 2 um thick SiGeB etch-stop layer, through 850C/12 h bond strengthening annealing and selective etching, to the final chemical-mechanical planarization (CMP) treatment. We have found that the device layer thickness is reduced during the annealing and selective tetramethylamonium hydroxide and HNA (mixture of hydrofluoric, nitric and acetic acids) etching processes. This thickness reduction was found to be 0.592 um, independently on the original device layer thickness. We have also found that the wafer surface is covered by a thin silicon suboxide layer after the HNA etching. The layer can be however easily removed by CMP with stock removal higher than 0.1um. Such process also polishes the wafer surface to prime quality micro-roughness. For studied BESOI process we therefore propose additional epitaxial growth of 0.8 um to the thickness target of the lightly doped epitaxial layer (future device layer) and using CMP stock removal of 0.2 um to obtain BESOI wafer with superior device layer surface micro-roughness and thickness uniformity.
dcterms:title
Optimization of the bond and etch-back silicon-on-insulator manufacturing processes Optimization of the bond and etch-back silicon-on-insulator manufacturing processes
skos:prefLabel
Optimization of the bond and etch-back silicon-on-insulator manufacturing processes Optimization of the bond and etch-back silicon-on-insulator manufacturing processes
skos:notation
RIV/26821532:_____/13:#0000034!RIV13-TA0-26821532
n6:predkladatel
n17:ico%3A26821532
n3:aktivita
n16:P
n3:aktivity
P(TA01010078)
n3:cisloPeriodika
6
n3:dodaniDat
n5:2013
n3:domaciTvurceVysledku
n9:6724264 n9:8906793
n3:druhVysledku
n13:J
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n15:predkladatel
n3:idSjednocenehoVysledku
94492
n3:idVysledku
RIV/26821532:_____/13:#0000034
n3:jazykVysledku
n18:eng
n3:klicovaSlova
SOI; Epitaxy; Selective Etching; CMP
n3:klicoveSlovo
n8:SOI n8:Selective%20Etching n8:CMP n8:Epitaxy
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[7BB608519F63]
n3:nazevZdroje
Advanced Science, Engineering and Medicine
n3:obor
n7:JJ
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n14:TA01010078
n3:rokUplatneniVysledku
n5:2013
n3:svazekPeriodika
5
n3:tvurceVysledku
Kostelník, Petr Šik, Jan
s:issn
2164-6627
s:numberOfPages
5