. . "Implementation of a Processor in a Field Programmable Gate Array"@en . "2"^^ . "Processor; coprocessor MIPS; RISC; FPGA"@en . . "RIV/68407700:21240/12:00204769" . . . . "I" . . . . "Implementace procesoru na programovateln\u00E9m hradlov\u00E9m poli"@cs . "Implementace procesoru na programovateln\u00E9m hradlov\u00E9m poli" . "http://users.fit.cvut.cz/~novotnym/projects/" . . "Implementation of a Processor in a Field Programmable Gate Array"@en . "Odhadovan\u00E1 cena 1000 K\u010D/instanci." . . . "IP core. Vlastn\u00EDkem v\u00FDsledku je \u010CVUT v Praze, I\u010C 68407700." . "Implementace procesoru na programovateln\u00E9m hradlov\u00E9m poli" . "Design and implementation of a processor based on a reduced MIPS32 architecture on FPGA. Instruction set of this processor can be extended by custom coprocessors. The processor implements only part of the MIPS32 instruction set neccessary for this project."@en . "Novotn\u00FD-DP-2012.01" . "N\u00E1vrh a implementace procesoru zalo\u017Een\u00E9ho na redukovan\u00E9 instruk\u010Dn\u00ED sad\u011B MIPS32 na FPGA. Instruk\u010Dn\u00ED sada tohoto procesoru je roz\u0161i\u0159iteln\u00E1 pou\u017Eit\u00EDm u\u017Eivatelsk\u00FDch koprocesor\u016F. Procesor implementuje pouze podmno\u017Einu instrukc\u00ED MIPS32 pot\u0159ebnou pro tento projekt." . . "Novotn\u00FD, Martin" . . . . . "N\u00E1vrh a implementace procesoru zalo\u017Een\u00E9ho na redukovan\u00E9 instruk\u010Dn\u00ED sad\u011B MIPS32 na FPGA. Instruk\u010Dn\u00ED sada tohoto procesoru je roz\u0161i\u0159iteln\u00E1 pou\u017Eit\u00EDm u\u017Eivatelsk\u00FDch koprocesor\u016F. Procesor implementuje pouze podmno\u017Einu instrukc\u00ED MIPS32 pot\u0159ebnou pro tento projekt."@cs . . "Prok\u0161, Michal" . "21240" . "140793" . "2"^^ . "RIV/68407700:21240/12:00204769!RIV13-MSM-21240___" . "Implementace procesoru na programovateln\u00E9m hradlov\u00E9m poli"@cs . . . "[01470E11A81B]" .