. "Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA" . "4"^^ . "Seville" . "Monterey" . "I, P(GAP103/12/2377)" . . . "linear systems; system of linear congruences; solver; FPGA"@en . . "The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension."@en . "Kubal\u00EDk, Pavel" . "The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension." . "978-1-4673-1261-5" . . "Zahradnick\u00FD, Tom\u00E1\u0161" . . . . "The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012" . . . "RIV/68407700:21240/12:00197211" . "Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA"@en . "10.1109/ICECS.2012.6463632" . "Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA" . . . "129806" . . . "Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA"@en . . . "4"^^ . . "2012-12-09+01:00"^^ . . "RIV/68407700:21240/12:00197211!RIV14-MSM-21240___" . . "L\u00F3rencz, R\u00F3bert" . "L\u00F3rencz, R\u00F3bert" . "IEEE Circuits and Systems Society" . "[51410F0BC368]" . . "21240" . . "Bu\u010Dek, Ji\u0159\u00ED" . "4"^^ .