"Softwarov\u00E9 j\u00E1dro procesoru ADOP"@cs . "Software. Zisk\u00E1n\u00ED: K\u010CN, FIT \u010CVUT v Praze. Vlastn\u00EDkem v\u00FDsledku je \u010CVUT v Praze, I\u010C 68407700." . "Kub\u00E1tov\u00E1, Hana" . "ADOP Soft-Core"@en . . . "Softwarov\u00E9 j\u00E1dro procesoru ADOP" . . "169049" . "Procesorov\u00E9 j\u00E1dro implementuje proudov\u00E9 zpracov\u00E1n\u00ED instrukc\u00ED v 5 stupn\u00EDch - IF, ID, MEM, EX, WB. A\u010Dkoli jm\u00E9na jednotliv\u00FDch stup\u0148\u016F jsou podobn\u00E1 standardn\u00ED 5-stup\u0148ov\u00E9 celo\u010D\u00EDseln\u00E9 RISC pipeline (nap\u0159. DLX, MIPS), po\u0159ad\u00ED stup\u0148\u016F a jejich vnit\u0159n\u00ED funkce je odli\u0161n\u00E1. Procesorov\u00E9 j\u00E1dro je naps\u00E1no ve VHDL, je snadno p\u0159enositeln\u00E9 a roz\u0161i\u0159iteln\u00E9 a p\u0159izp\u016Fsobiteln\u00E9 pro konkr\u00E9tn\u00ED implementaci v FPGA."@cs . "Softwarov\u00E9 j\u00E1dro procesoru ADOP" . "http://ddd.fit.cvut.cz/" . . . "ADOP soft-core implements 5 stage pipe-line - IF, ID, MEM, EX, WB - with different internal functions version Rev3. ADOP soft core is created in synthesible VHDL. The concrete implementation for different types of FPGA is straightforward."@en . . "Novotn\u00FD, Martin" . "RIV/68407700:21240/12:00191564!RIV13-MSM-21240___" . . . . "RIV/68407700:21240/12:00191564" . . . . "[FB2641DDDFA9]" . . . . . "ADOP Soft-Core"@en . "Be\u010Dv\u00E1\u0159, Milo\u0161" . . . "SW je vyvinut\u00FD pro v\u00FDukov\u00E9 \u00FA\u010Dely, ale je pou\u017Eiteln\u00FD jako standardn\u00ED procesorov\u00E9 j\u00E1dro." . "3"^^ . "Procesorov\u00E9 j\u00E1dro implementuje proudov\u00E9 zpracov\u00E1n\u00ED instrukc\u00ED v 5 stupn\u00EDch - IF, ID, MEM, EX, WB. A\u010Dkoli jm\u00E9na jednotliv\u00FDch stup\u0148\u016F jsou podobn\u00E1 standardn\u00ED 5-stup\u0148ov\u00E9 celo\u010D\u00EDseln\u00E9 RISC pipeline (nap\u0159. DLX, MIPS), po\u0159ad\u00ED stup\u0148\u016F a jejich vnit\u0159n\u00ED funkce je odli\u0161n\u00E1. Procesorov\u00E9 j\u00E1dro je naps\u00E1no ve VHDL, je snadno p\u0159enositeln\u00E9 a roz\u0161i\u0159iteln\u00E9 a p\u0159izp\u016Fsobiteln\u00E9 pro konkr\u00E9tn\u00ED implementaci v FPGA." . . "procesor; pipe-lining; soft-core; programmable hardware; FPGA"@en . "3"^^ . "Z(MSM6840770014)" . "21240" . . "ADOP-VHDL soft-core" . "Softwarov\u00E9 j\u00E1dro procesoru ADOP"@cs . . .