"IEEE Computer Society Press" . "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints"@en . . . "Lemberski, I." . . "Proceedings of the 13th Euromicro Conference on Digital System Design" . . . "978-0-7695-4171-6" . . . "RIV/68407700:21240/10:00169329" . . "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints" . . "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints"@en . "Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2 input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose." . "1"^^ . . . "asynchronous circuits, DIMS, direct logic, NCL"@en . "2"^^ . "247706" . . "[71AF075FFC47]" . "2010-09-01+02:00"^^ . "Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints" . . . "Fi\u0161er, Petr" . . . . . "Los Alamitos" . "P(GA102/09/1668), Z(MSM6840770014)" . "21240" . "8"^^ . "Lille" . "Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2 input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose."@en . "RIV/68407700:21240/10:00169329!RIV11-GA0-21240___" . .