"V\u00FDsledkem t\u00E9to pr\u00E1ce je VHDL k\u00F3d p\u0159elo\u017Een\u00FD pro existuj\u00EDc\u00ED \u0159\u00EDdic\u00ED desku umo\u017E\u0148uj\u00EDc\u00ED zpracov\u00E1vat r\u00E1mce z ethernetu, radia a procesoru. \u0158\u00EDdic\u00ED deska v\u010Detn\u011B obslu\u017En\u00E9ho software mus\u00ED umo\u017E\u0148ovat sm\u011Brovat r\u00E1mce. FPGA obvod um\u00EDst\u011Bn\u00FD na \u0159\u00EDdic\u00ED desce propojuje 4 z\u00E1kladn\u00ED prvky zpracov\u00E1vaj\u00EDc\u00ED r\u00E1mce. Tyto prvky jsou: ethernetov\u00E9 rozhran\u00ED GMII, extern\u00ED sb\u011Brnice procesoru HD6417760, 4 bitov\u00E9 rozhran\u00ED sm\u011Brem k radiov\u00E9 desce a pam\u011B\u0165ov\u00E9 rozhran\u00ED pou\u017E\u00EDvan\u00E9 k vyrovn\u00E1van\u00ED rychlost\u00ED mezi ethernetem a radiem."@cs . . . "RIV/68407700:21240/09:00165731!RIV13-MSM-21240___" . "V\u00FDsledkem t\u00E9to pr\u00E1ce je VHDL k\u00F3d p\u0159elo\u017Een\u00FD pro existuj\u00EDc\u00ED \u0159\u00EDdic\u00ED desku umo\u017E\u0148uj\u00EDc\u00ED zpracov\u00E1vat r\u00E1mce z ethernetu, radia a procesoru. \u0158\u00EDdic\u00ED deska v\u010Detn\u011B obslu\u017En\u00E9ho software mus\u00ED umo\u017E\u0148ovat sm\u011Brovat r\u00E1mce. FPGA obvod um\u00EDst\u011Bn\u00FD na \u0159\u00EDdic\u00ED desce propojuje 4 z\u00E1kladn\u00ED prvky zpracov\u00E1vaj\u00EDc\u00ED r\u00E1mce. Tyto prvky jsou: ethernetov\u00E9 rozhran\u00ED GMII, extern\u00ED sb\u011Brnice procesoru HD6417760, 4 bitov\u00E9 rozhran\u00ED sm\u011Brem k radiov\u00E9 desce a pam\u011B\u0165ov\u00E9 rozhran\u00ED pou\u017E\u00EDvan\u00E9 k vyrovn\u00E1van\u00ED rychlost\u00ED mezi ethernetem a radiem." . . . "1"^^ . "339381" . "1"^^ . . "2009-xkubalik-SVM" . "VHDL implementace" . "\u0158\u00EDdic\u00ED software pro zpracov\u00E1n\u00ED ethernetov\u00FDch r\u00E1mc\u016F ur\u010Den\u00FDch k p\u0159enosu s pomoc\u00ED mikrovlnn\u00E9ho radiov\u00E9ho spoje" . . "Z(MSM6840770014)" . . "Kubal\u00EDk, Pavel" . . "\u0158\u00EDdic\u00ED software pro zpracov\u00E1n\u00ED ethernetov\u00FDch r\u00E1mc\u016F ur\u010Den\u00FDch k p\u0159enosu s pomoc\u00ED mikrovlnn\u00E9ho radiov\u00E9ho spoje" . . "Application software for control system device allowing Ethernet packet preprocessing and routing"@en . . . "21240" . . . "\u0158\u00EDdic\u00ED software pro zpracov\u00E1n\u00ED ethernetov\u00FDch r\u00E1mc\u016F ur\u010Den\u00FDch k p\u0159enosu s pomoc\u00ED mikrovlnn\u00E9ho radiov\u00E9ho spoje"@cs . . "http://users.fit.cvut.cz/xkubalik" . . "\u0158\u00EDdic\u00ED software pro zpracov\u00E1n\u00ED ethernetov\u00FDch r\u00E1mc\u016F ur\u010Den\u00FDch k p\u0159enosu s pomoc\u00ED mikrovlnn\u00E9ho radiov\u00E9ho spoje"@cs . "100000CZK" . "RIV/68407700:21240/09:00165731" . . "Application software for control system device allowing Ethernet packet preprocessing and routing"@en . "Final implementation of control system was created. Implementation is based on VHDL source code. System enable route packet between four interfaces. These interfaces are: Ethernet core, external memory core, processor and radio interface. System finally operates at 125 MHz clock speed."@en . "FPGA; VHDL Language"@en . "[CAE9D0DE18B6]" .