"RIV/68407700:21230/08:03144365" . "Dependable design technique for system-on-chip"@en . "2008" . . "Journal of Systems Architecture" . "A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters."@cs . . . "1383-7621" . "Dependable design technique for system-on-chip" . "54" . "Metodologie spolehliveho navrhu pro systemy na cipu"@cs . . "362519" . "000256705500009" . . . . . "A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters."@en . "2"^^ . "Metodologie spolehliveho navrhu pro systemy na cipu"@cs . . "Dependable design technique for system-on-chip"@en . . "Fault security; Self-testing; Totally selfchecking; Reliable digital design; FPGA; Dependability model; Dependability calculations; On-line testing"@en . . "A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters." . . "RIV/68407700:21230/08:03144365!RIV09-MSM-21230___" . "2"^^ . "Dependable design technique for system-on-chip" . "13"^^ . . . "NL - Nizozemsko" . "21230" . "Kub\u00E1tov\u00E1, Hana" . "Kubal\u00EDk, Pavel" . "Z(MSM6840770014)" . "[D080CC39C69D]" . . . . . . . .