. "[FD43EA1E8609]" . "Experimental SEU Impact on Digital Design Implemented in FPGAs"@en . "Experimental SEU Impact on Digital Design Implemented in FPGAs"@en . . . "Proceedings of 11th Euromicro Conference on Digital System Design" . . "2008-09-03+02:00"^^ . "Parma" . . . "367225" . . "2"^^ . . "Experimental SEU Impact on Digital Design Implemented in FPGAs" . "Los Alamitos" . "Kub\u00E1tov\u00E1, Hana" . "000264279400014" . . "The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture."@en . . "RIV/68407700:21230/08:00147000" . "RIV/68407700:21230/08:00147000!RIV10-MSM-21230___" . . "3"^^ . "Kubal\u00EDk, Pavel" . . "The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture." . . "21230" . . "P(FI-IM4/149), Z(MSM6840770014)" . "978-0-7695-3277-6" . . "FPGA; dependability; fault emulator; fault model; single event upset"@en . . . . "Experimental SEU Impact on Digital Design Implemented in FPGAs" . "4"^^ . . "IEEE Computer Society" . . .