"An FPGA hardware fault emulator is presented. The emulator performs a single-bit fault injection in bitstream on top of the implemented circuit, emulating the SEU event. The combinatorial circuits mapped in FPGA are tested and SEU-fault resistance is observed."@en . "An FPGA based fault emulator"@en . "3"^^ . . . "An FPGA based fault emulator"@cs . . "Z(MSM6840770014)" . "Johannes Kepler University" . "RIV/68407700:21230/07:03133257!RIV08-MSM-21230___" . "3"^^ . . . . . . "L\u00FCbeck" . . . "An FPGA based fault emulator" . "[F18CC07671AA]" . "409322" . "FPGA, fault emulator, fault injection, simulation, single-event-upset"@en . "21230" . . "Kub\u00E1tov\u00E1, Hana" . "2007-08-27+02:00"^^ . "An FPGA hardware fault emulator is presented. The emulator performs a single-bit fault injection in bitstream on top of the implemented circuit, emulating the SEU event. The combinatorial circuits mapped in FPGA are tested and SEU-fault resistance is observed." . . "An FPGA based fault emulator"@en . . . "42;43" . "RIV/68407700:21230/07:03133257" . "An FPGA based fault emulator" . "Kubal\u00EDk, Pavel" . . . "Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007" . "An FPGA hardware fault emulator is presented. The emulator performs a single-bit fault injection in bitstream on top of the implemented circuit, emulating the SEU event. The combinatorial circuits mapped in FPGA are tested and SEU-fault resistance is observed."@cs . "Linz" . "2"^^ . "An FPGA based fault emulator"@cs . . . "Kvasni\u010Dka, Ji\u0159\u00ED" . . . "978-3-902457-16-5" .