. "Popis metody injekce a simulace poruch pro rekonfigurovateln\u00FD duplexn\u00ED syst\u00E9m odoln\u00FD proti poruch\u00E1m."@cs . . "421744" . . "Injekce a simulace poruch pro rekonfigurovateln\u00FD duplexn\u00ED syst\u00E9m odoln\u00FD proti poruch\u00E1m"@cs . . "Kub\u00E1tov\u00E1, Hana" . . "Z(MSM6840770014)" . . "1-4244-1161-0" . "Injekce a simulace poruch pro rekonfigurovateln\u00FD duplexn\u00ED syst\u00E9m odoln\u00FD proti poruch\u00E1m"@cs . "Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System"@en . "Kubal\u00EDk, Pavel" . . . . "3"^^ . . "Kvasni\u010Dka, Ji\u0159\u00ED" . . "3"^^ . "357;360" . "The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed." . . "Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System" . . . . "Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System" . . "hardware fault emulation, fault tolerant design, digital design"@en . . "RIV/68407700:21230/07:03130529!RIV08-MSM-21230___" . "4"^^ . "RIV/68407700:21230/07:03130529" . "2007-04-10+02:00"^^ . "Krakow" . "Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System"@en . "21230" . "IEEE Computer Society" . "[FABBBD7CF31A]" . "The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed."@en . "Design and Diagnostics of Electronic Circuits and Systems" . "Los Alamitos" . .