"Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium" . . . "This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults." . "RIV/68407700:21230/06:03120136" . "Fault Tolerant System Design Method Based on Self-Checking Circuits"@en . "Fault Tolerant System Design Method Based on Self-Checking Circuits"@en . . "Fault Tolerant System Design Method Based on Self-Checking Circuits" . "3"^^ . "Fi1er, Petr" . . . "Los Alamitos" . "475636" . "2"^^ . "Kub\u00E1tov\u00E1, Hana" . . . "0-7695-2620-9" . "Kubal\u00EDk, Pavel" . "RIV/68407700:21230/06:03120136!RIV07-GA0-21230___" . "2006-07-10+02:00"^^ . . "IEEE Computer Society" . "3"^^ . "185 ; 186" . . . "[196F9C688A93]" . . . . . . "21230" . . "P(GA102/04/0737), Z(MSM6840770014)" . "Fault Tolerant System Design Method Based on Self-Checking Circuits" . "FPGA, reconfiguration, fault tolerance, self-checking circuit"@en . "This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults."@cs . "Como" . . . . . . "This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults."@en . "Fault Tolerant System Design Method Based on Self-Checking Circuits"@cs . "Fault Tolerant System Design Method Based on Self-Checking Circuits"@cs .