. . "Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics" . . "\u0160\u0165\u00E1va, Martin" . "RIV/68407700:21230/06:03119432!RIV07-GA0-21230___" . "21230" . . "Rekonfigurace backtrace algoritmu implementovan\u00E9ho v HW pro zrychlen\u00ED procesu generov\u00E1n\u00ED vektoru"@cs . "Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process"@en . "2006-05-25+02:00"^^ . . "Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %)." . . . "6"^^ . "Our backward-determining structure generates all valid input vectors to an applied output vector, an input vector is generated during only one clock cycle, two variants of reconfiguration for speeding up the vector generation, experimental data obtained for ISCAS'85. Reconfiguration usage for small circuits is not effective enough (average area overhead is about 120 %, average speed up is about 9.3 %), but for large circuits is acceptable (average area overhead is about 96 %, average speed up is about 21.5 %)."@en . . . . "P(GA102/04/2137), Z(MSM6840770014)" . "IEEE" . "1-4244-0360-X" . . "Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process" . "Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process"@en . "59 ; 64" . . "Piscataway" . "[FF7567632EF7]" . . "496734" . . "2"^^ . . "Nov\u00E1k, Ond\u0159ej" . . "Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process" . . "2"^^ . . "Rekonfigurace backtrace algoritmu implementovan\u00E9ho v HW pro zrychlen\u00ED procesu generov\u00E1n\u00ED vektoru"@cs . "backtrace; hardware; reconfiguration; scan design; vector generation"@en . "N\u00E1mi navr3en\u00E1 zpitni-odvozuj\u00EDc\u00ED struktura generuje v1echny platn\u00E9 vstupn\u00ED vektory k poilo3en\u00E9mu v\u00FDstupn\u00EDmu vektoru, vstupn\u00ED vektor je generov\u00E1n bihem pouze jednoho hodinov\u00E9ho cyklu, dvi varianty rekonfigurace pro zrychlen\u00ED generov\u00E1n\u00ED vektoru, experiment\u00E1ln\u00ED data z\u00EDsk\u00E1na nad ISCAS'85. Vyu3it\u00ED rekonfigurace pro mal\u00E9 obvody nen\u00ED dostateeni efektivn\u00ED (prumirn\u00E1 prostorov\u00E1 slo3itost je okolo 120 %, prumirn\u00E9 zrychlen\u00ED je v1ak pouze okolo 9,3 %), ale pro velk\u00E9 obvody je poijateln\u00FD (prumirn\u00E1 prostorov\u00E1 slo3itost je okolo 96 %, prumirn\u00E9 zrychlen\u00ED je okolo 21,5 %)."@cs . . "RIV/68407700:21230/06:03119432" . . . "Cluj-Napoca" .