. "A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation"@en . "Nov\u00E1k, Ond\u0159ej" . . . . "Model struktury pro odvozov\u00E1n\u00ED vstupn\u00EDch vektoru kombinaen\u00EDch obvodu a jeho simulace"@cs . "backtrace; digital circuit; hardware; modelling; simulation"@en . . "2006-04-25+02:00"^^ . . . "A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation" . "80-86840-21-2" . . . . "A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation"@en . "2"^^ . . . . "51 ; 57" . "2"^^ . "RIV/68407700:21230/06:03119426" . . "RIV/68407700:21230/06:03119426!RIV07-GA0-21230___" . "Model struktury pro odvozov\u00E1n\u00ED vstupn\u00EDch vektoru kombinaen\u00EDch obvodu a jeho simulace"@cs . "\u0160\u0165\u00E1va, Martin" . "[D2C69364102B]" . "463847" . "Poerov" . . . "A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation" . . . "7"^^ . "The backtrace models implemented in hardware and simulation of one of them are presented. These models perform input vector derivation of any combinational circuit part on the basis of the output vector knowledge and constraints. In this paper we introduce two different models serving as backtrace units. The behavioural models have been described in the language VHDL."@en . "21230" . "Presentuje backtrace modely implementovan\u00E9 v hardwaru a simulaci jednoho z nich. Oba tyto modely prov\u00E1dij\u00ED odvozov\u00E1n\u00ED vstupn\u00EDho vektoru jak\u00E9koliv e\u00E1sti kombinaen\u00EDho obvodu na z\u00E1kladi znalosti v\u00FDstupn\u00EDho vektoru a omezuj\u00EDc\u00EDch podm\u00EDnek. Jsou zde uvedeny dva odli1n\u00E9 modely slou3\u00EDc\u00ED jako backtrace jednotky. Modely na \u00FArovni popisu chov\u00E1n\u00ED byly zaps\u00E1ny v jazyku VHDL."@cs . . "Ostrava" . "MARQ" . "Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems" . . . "The backtrace models implemented in hardware and simulation of one of them are presented. These models perform input vector derivation of any combinational circuit part on the basis of the output vector knowledge and constraints. In this paper we introduce two different models serving as backtrace units. The behavioural models have been described in the language VHDL." . "P(GA102/04/2137), Z(MSM6840770014)" .