. "Ostrava" . . . "21230" . "Representation of Logical Circuits and Parser with Layer Architecture Allowing to Be Easily Adapted"@en . "\u0160\u0165\u00E1va, Martin" . "Proceedings of XXVIII-th International Autumn Colloquium ASIS 2006" . "Representation of Logical Circuits and Parser with Layer Architecture Allowing to Be Easily Adapted" . . "circuit model; layer architecture; logic circuit; parser"@en . "6"^^ . . "[3503A45078FD]" . "Vranov (u Brna)" . "A developed flexible internal representation of logical circuits and an layer architecture of a parser, which loads circuits in ISCAS format into the internal representation, are presented. Described representation and parser allow to be easily and quickly modified as necessary and have been successfully used in three programs."@en . "MARQ" . . "497274" . . . "A developed flexible internal representation of logical circuits and an layer architecture of a parser, which loads circuits in ISCAS format into the internal representation, are presented. Described representation and parser allow to be easily and quickly modified as necessary and have been successfully used in three programs." . . "Representation of Logical Circuits and Parser with Layer Architecture Allowing to Be Easily Adapted" . . . "2006-09-12+02:00"^^ . "2"^^ . . "80-86840-26-3" . "RIV/68407700:21230/06:00120654!RIV10-MSM-21230___" . "V" . . "Representation of Logical Circuits and Parser with Layer Architecture Allowing to Be Easily Adapted"@en . . "1"^^ . "RIV/68407700:21230/06:00120654" . . .