"Acta Polytechnica" . . "This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented."@cs . . "RIV/68407700:21230/05:03117292!RIV06-MSM-21230___" . . "6" . "2"^^ . . . "Parity Codes Used for On-line Testing in FPGA" . "2"^^ . "Parity Codes Used for On-line Testing in FPGA"@cs . "1210-2709" . "RIV/68407700:21230/05:03117292" . "Z(MSM6840770014)" . . "45" . "Parity Codes Used for On-line Testing in FPGA"@en . "Kub\u00E1tov\u00E1, Hana" . "On-line testing, self-checking, error detection code, fault, error, FPGA"@en . . "Parity Codes Used for On-line Testing in FPGA" . . . "535439" . "This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented."@en . . "Kubal\u00EDk, Pavel" . "CZ - \u010Cesk\u00E1 republika" . "21230" . "This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes. The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented." . . . "7"^^ . . "[6DF0B0D7A410]" . "Parity Codes Used for On-line Testing in FPGA"@cs . . . . . "53 ; 59" . . "Parity Codes Used for On-line Testing in FPGA"@en . .