. "530410" . . . . "Mixed-Mode BIST zalo\u017Een\u00FD na Column Matching algoritmu"@cs . "[8DFC5333BDE3]" . . "45 ; 50" . "P(GA102/04/2137)" . "Po\u010D\u00EDta\u010Dov\u00E9 architektury & diagnostika" . "Fi\u0161er, Petr" . "L\u00E1zn\u011B Sedmihorky" . "built-in self-test; diagnostics; logic synthesis; test generation"@en . "1"^^ . "Nen\u00ED k dispozici"@cs . . "2005-09-21+02:00"^^ . "1"^^ . . . "Mixed-Mode BIST Based on Column Matching"@en . . "A test-per-clock BIST method for combinational or full-scan circuits is proposed. The method is based on a design of a combinational block - the decoder, transforming pseudo-random LFSR code words into deterministic test patterns. A Column-Matching algorithm to design the decoder is proposed. The Column Matching method modified to support a mixed-mode BIST is proposed as well. Here the BIST is divided into two disjoint phases - the pseudo-random phase, where the LFSR patterns are being applied to the circuit unmodified, and the deterministic phase detecting all the yet undetected faults. This enables us to reach a high fault coverage in a short test time and with a low area overhead."@en . . "Mixed-Mode BIST Based on Column Matching"@en . . . "80-01-03298-1" . "\u010Cesk\u00E9 vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Praze. Fakulta elektrotechnick\u00E1. Katedra po\u010D\u00EDta\u010D\u016F" . "Praha" . "21230" . . "6"^^ . . . "RIV/68407700:21230/05:03113895!RIV06-GA0-21230___" . "Mixed-Mode BIST zalo\u017Een\u00FD na Column Matching algoritmu"@cs . . "RIV/68407700:21230/05:03113895" . "Mixed-Mode BIST Based on Column Matching" . "Mixed-Mode BIST Based on Column Matching" . . "A test-per-clock BIST method for combinational or full-scan circuits is proposed. The method is based on a design of a combinational block - the decoder, transforming pseudo-random LFSR code words into deterministic test patterns. A Column-Matching algorithm to design the decoder is proposed. The Column Matching method modified to support a mixed-mode BIST is proposed as well. Here the BIST is divided into two disjoint phases - the pseudo-random phase, where the LFSR patterns are being applied to the circuit unmodified, and the deterministic phase detecting all the yet undetected faults. This enables us to reach a high fault coverage in a short test time and with a low area overhead." .