"Po\u010D\u00EDta\u010Dov\u00E9 architektury & diagnostika" . "Highly Reliable Design Based on TSC Circuits"@en . . . "Kub\u00E1tov\u00E1, Hana" . "Vysoce spolehliv\u00FD n\u00E1vrh TSC obvod\u016F"@cs . "Highly Reliable Design Based on TSC Circuits"@en . . "RIV/68407700:21230/05:03109967!RIV06-GA0-21230___" . "21230" . . "101 ; 106" . "Vysoce spolehliv\u00FD n\u00E1vrh TSC obvod\u016F"@cs . . "6"^^ . "RIV/68407700:21230/05:03109967" . . . "2"^^ . . "523314" . "\u010Cl\u00E1nek se zab\u00FDva n\u00E1vrhem vysoce spolehliv\u00FDch obvod implementovan\u00FDch pomoc\u00ED FPGA obvod\u016F. N\u00E1vrh je zalo\u017Een na jednoduch\u00E9m zdvojen\u00ED obvod\u016F spl\u0148uj\u00EDc\u00EDch podminky pro n\u00E1vrh TSC obvodu."@cs . "2"^^ . "Highly Reliable Design Based on TSC Circuits" . . "Praha" . "This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools."@en . . . . "2005-09-21+02:00"^^ . . "P(GA102/03/0672), Z(MSM6840770014)" . . . "[10459FE9436E]" . . "\u010Cesk\u00E9 vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Praze. Fakulta elektrotechnick\u00E1. Katedra po\u010D\u00EDta\u010D\u016F" . "Kubal\u00EDk, Pavel" . . . "This paper deals with architecture of highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. A duplex system is used as a basic structure of this reliable design. The whole design implemented in FPGA is divided into individual functional parts. Every part is modified to ensure totally self checking properties, which are calculated using our method of detailed fault classification. The reconfiguration process is utilized to increase reliability parameters. Combinational circuit benchmarks have been considered in this work to compute the quality of the adapted duplex system. The benchmarks are represented by two level networks (truth table). All of our experimental results are obtained by XILINX FPGA implementation by EDA tools." . "FPGA, tottaly self-checking (TSC) circuit, dependability, concurrent error detection (CED)"@en . "Highly Reliable Design Based on TSC Circuits" . . "L\u00E1zn\u011B Sedmihorky" . "80-01-03298-1" . .