"backtrace; backtrack; hardware; logic simulation; synchronisation"@en . "A Logic Simulation for the Input Vectors Derivation of a Combinational Logic Circuit by HW"@en . . . . "Nov\u00E1k, Ond\u0159ej" . "21230" . . "Zp\u011Btn\u00E1 logick\u00E1 simulace, zp\u011Btn\u00E9 odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu zalo\u017Een\u00E9 na znalosti v\u00FDstupn\u00EDch vektor\u016F pomoc\u00ED HW. Simula\u010Dn\u00ED proces je pops\u00E1n v jazyku VHDL."@cs . . . "Backward logic simulation, the input vectors derivation of a combinational logic circuit based on output vectors knowledge by HW. A simulation process is described in VHDL."@en . . . . . . "Zp\u011Btn\u00E1 logick\u00E1 simulace pro odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu pomoc\u00ED HW"@cs . "6"^^ . . . . "2005-09-06+02:00"^^ . "MARQ" . "P\u0159erov" . "552448" . "A Logic Simulation for the Input Vectors Derivation of a Combinational Logic Circuit by HW"@en . . "2"^^ . "\u0160\u0165\u00E1va, Martin" . . "Proceedings of XXVII International Autumn Colloquium" . "215 ; 220" . . "Zp\u011Btn\u00E1 logick\u00E1 simulace pro odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu pomoc\u00ED HW"@cs . "2"^^ . "Zp\u011Btn\u00E1 logick\u00E1 simulace pro odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu pomoc\u00ED HW" . "Zp\u011Btn\u00E1 logick\u00E1 simulace, zp\u011Btn\u00E9 odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu zalo\u017Een\u00E9 na znalosti v\u00FDstupn\u00EDch vektor\u016F pomoc\u00ED HW. Simula\u010Dn\u00ED proces je pops\u00E1n v jazyku VHDL." . "P(GA102/04/2137), Z(MSM6840770014)" . "[0D39CFFBCC90]" . "80-86840-16-6" . "Zp\u011Btn\u00E1 logick\u00E1 simulace pro odvozen\u00ED vstupn\u00EDch vektor\u016F kombina\u010Dn\u00EDho obvodu pomoc\u00ED HW" . . "RIV/68407700:21230/05:03109949!RIV06-GA0-21230___" . "Ostrava" . . . "RIV/68407700:21230/05:03109949" . .