. . . . "228 ; 231" . . "Kub\u00E1tov\u00E1, Hana" . "Fault Classification for Self-checking Circuits Implemented in FPGA" . "4"^^ . . . "Nov\u00E1k, Ond\u0159ej" . . . "Kubal\u00EDk, Pavel" . "RIV/68407700:21230/05:03108032!RIV06-GA0-21230___" . . "fault security, self-testing, fault tolerant,, digital design. testing, FPGA"@en . . "Nen\u00ED k dispozici"@cs . "RIV/68407700:21230/05:03108032" . . . "521445" . "Fault Classification for Self-checking Circuits Implemented in FPGA"@en . "Nen\u00ED k dispozici"@cs . "Sopron" . . "Nen\u00ED k dispozici"@cs . "2005-04-13+02:00"^^ . . "Sopron" . "University of Western Hungary" . "21230" . "Fault Classification for Self-checking Circuits Implemented in FPGA"@en . . "Kafka, Leo\u0161" . "Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop" . "This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered." . . . "Fault Classification for Self-checking Circuits Implemented in FPGA" . "This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups - the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered."@en . . "[D7866F3DC291]" . "4"^^ . "963-9364-48-7" . . "4"^^ . . . "P(GA102/04/2137), Z(MSM6840770014)" . .