. "Kubal\u00EDk, Pavel" . "564217" . "P(GA102/04/2137), Z(MSM 212300014)" . . "Nen\u00ED k dispozici"@cs . "Fault Tolerant Design Methodology"@en . "Fault Tolerant Design Methodology" . . . "RIV/68407700:21230/04:03107162" . "FPGA, on-line testing, fault-tolerance, error detection codes"@en . . "This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit." . . "Fault Tolerant Design Methodology"@en . "1"^^ . "neuvedeno" . . "This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation. Due to their further implementation in FPGAs the fault model considers that the configuration data are stored in the configuration memory. This work is a part of a more complex methodology of a fault tolerant design based on FPGAs with dynamical reconfiguration of the faulty part of the designed circuit."@en . "Nen\u00ED k dispozici"@cs . . "[B578399FEBD9]" . "1"^^ . "Fault Tolerant Design Methodology" . . . "Nen\u00ED k dispozici"@cs . "Praha" . . . . . . . . . "21230" . . "RIV/68407700:21230/04:03107162!RIV/2005/GA0/212305/N" .