. "Tallinn Technical University" . "2"^^ . "[9EB4679DECA6]" . . . . "2"^^ . . . "Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST" . . "9985-59-462-2" . "Proceedings of the 9th Biennial Baltic Electronics Conference" . "21230" . "Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST" . . "Nen\u00ED k dispozici"@cs . "RIV/68407700:21230/04:03100099!RIV/2005/GA0/212305/N" . "Nen\u00ED k dispozici"@cs . "2004-10-03+02:00"^^ . "201 ; 204" . . "568059" . "Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST"@en . . . "Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST"@en . "Fi\u0161er, Petr" . "P(GA102/04/2137), Z(MSM 212300014)" . . . "Nen\u00ED k dispozici"@cs . "Kub\u00E1tov\u00E1, Hana" . . . "In this paper we present a discussion on choosing the test lengths in our mixed-mode BIST technique. The BIST design method is based on the column-matching algorithm proposed before. The mixed-mode strategy divides the test sequence into two disjoint phases: first the pseudo random phase detects the easy-to-detect faults, and the subsequent deterministic phase generates test vectors needed to fully test the circuit. The lengths of these two phases directly influence both the test time and the BIST area overhead, as well as the BIST design time. Some kind of trade-off has to be found, to design the BIST circuitry efficiently. The pseudo-random testability of the ISCAS benchmarks is studied here. The conclusions obtained here can be generalized to be applied to any circuit." . "4"^^ . . . . "Tallinn" . . "RIV/68407700:21230/04:03100099" . "Tallinn" . . "digital testing, mixed-mode BIST, test length, area overhead"@en . "In this paper we present a discussion on choosing the test lengths in our mixed-mode BIST technique. The BIST design method is based on the column-matching algorithm proposed before. The mixed-mode strategy divides the test sequence into two disjoint phases: first the pseudo random phase detects the easy-to-detect faults, and the subsequent deterministic phase generates test vectors needed to fully test the circuit. The lengths of these two phases directly influence both the test time and the BIST area overhead, as well as the BIST design time. Some kind of trade-off has to be found, to design the BIST circuitry efficiently. The pseudo-random testability of the ISCAS benchmarks is studied here. The conclusions obtained here can be generalized to be applied to any circuit."@en .