. "Minimization of the Hamming Code Generator in Self Checking Circuits"@en . "21230" . . "University of Zielona Gora" . . . . . . "Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04" . "RIV/68407700:21230/04:03099879" . "Nen\u00ED k dispozici"@cs . "The paper focuses on the minimization of the area overhead of check bits generator in the online BIST for circuits implemented in FPGAs. We have used error detection codes (ED codes) to ensure the self-checking property. The newly proposed simplification method consists of converting the duplicate circuit into a two-level network, for which the check-bits are generated. Then the outputs of the circuit are reduced to these check-bits only; the original outputs can be omitted. After that, a multi-level network is synthesized for this circuit. This notion enables us to significantly reduce the resulting logic." . . . . "P(GA102/04/2137), Z(MSM 212300014)" . . "Zielona Gora" . "Fi\u0161er, Petr" . "6"^^ . "83-89712-15-6" . . "FPGA, Built-In Self-Test (BIST), on-line, error detecting codes, self-checking circuit, totally self"@en . "161 ; 166" . "The paper focuses on the minimization of the area overhead of check bits generator in the online BIST for circuits implemented in FPGAs. We have used error detection codes (ED codes) to ensure the self-checking property. The newly proposed simplification method consists of converting the duplicate circuit into a two-level network, for which the check-bits are generated. Then the outputs of the circuit are reduced to these check-bits only; the original outputs can be omitted. After that, a multi-level network is synthesized for this circuit. This notion enables us to significantly reduce the resulting logic."@en . . "Kubal\u00EDk, Pavel" . "Minimization of the Hamming Code Generator in Self Checking Circuits"@en . "573726" . . "Nen\u00ED k dispozici"@cs . "Kub\u00E1tov\u00E1, Hana" . "2004-09-15+02:00"^^ . . . . . . "Nen\u00ED k dispozici"@cs . . "Dychow" . . . "Minimization of the Hamming Code Generator in Self Checking Circuits" . . "3"^^ . "RIV/68407700:21230/04:03099879!RIV/2005/GA0/212305/N" . "Minimization of the Hamming Code Generator in Self Checking Circuits" . "3"^^ . "[0452A1AE8517]" .