. . "Not available" . "RIV/68407700:21230/02:03074985!RIV/2003/MSM/212303/N" . "2002-09-15+02:00"^^ . "Integrated Timing-Driven Approach to the FPGA Layout"@en . . . . . . "693;696" . "FPGA; integrated approach; physical design algorithms; placement; routing"@en . "Piscataway" . . . . "2"^^ . "Not available"@en . "Integrated Timing-Driven Approach to the FPGA Layout" . "[4EB75D21DCB8]" . "0"^^ . "RIV/68407700:21230/02:03074985" . "0"^^ . "2"^^ . "Integrated Timing-Driven Approach to the FPGA Layout"@en . . "IEEE" . . "21230" . . "0-7803-7596-3" . "649316" . "The 9th IEEE International Conference on Electronics, Circuits and Systems" . "Z(MSM 212300014)" . "4"^^ . . "Dubrovnik" . . . . "Integrated Timing-Driven Approach to the FPGA Layout" . "Dan\u011Bk, Martin" . .