"[ED5F06249C81]" . "8"^^ . . . "Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012" . . "Reducing Instruction Issue Overheads in Application-Specific Vector Processors"@en . "4"^^ . "S\u00FDkora, Jaroslav" . "RIV/67985556:_____/12:00380442!RIV13-MSM-67985556" . "Izmir" . . "Honz\u00EDk, P." . . "The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table." . "Reducing Instruction Issue Overheads in Application-Specific Vector Processors" . . "RIV/67985556:_____/12:00380442" . . . "The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm. In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table."@en . "5"^^ . "Reducing Instruction Issue Overheads in Application-Specific Vector Processors"@en . "P(7H10001)" . . "Dan\u011Bk, Martin" . "Conference Publishing Services" . . "978-0-7695-4798-5" . . . "164483" . "Bartosinski, Roman" . . "2012-09-05+02:00"^^ . . . . "custom accelerators; vector processing; FPGA; DSP"@en . "Cesme" . . . . "Kohout, Luk\u00E1\u0161" . . "Reducing Instruction Issue Overheads in Application-Specific Vector Processors" . .