. "RIV/67985556:_____/11:00363078!RIV12-AV0-67985556" . "RIV/67985556:_____/11:00363078" . "978-1-4577-0537-3" . . "The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator" . . . . "LDU decomposition; directional forgetting; hardware accelerator"@en . . . . . "Praha" . "Praha" . "4"^^ . . "209083" . "Bartosinski, Roman" . . "IEEE" . . "The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator"@en . "The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator"@en . "2011-05-22+02:00"^^ . . "[DBAF4B2513E8]" . "1"^^ . . "P(7H10001), Z(AV0Z10750506)" . "1"^^ . "ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing" . "The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform."@en . . "The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator" . . . "The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform." . . .