. . "Traditional design techniques for FPGAs are based on using hardware description languages, with functional and postplace-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations."@en . . . "Increasing the Level of Abstraction in FPGA-based Designes"@en . . . "RIV/67985556:_____/08:00313274!RIV09-AV0-67985556" . "Heidelberg" . "Dan\u011Bk, Martin" . . "RIV/67985556:_____/08:00313274" . "[28638DC43319]" . "Heidelberg" . . . . . "Kirchhoff Institute for Physics" . "Kohout, Luk\u00E1\u0161" . . "6"^^ . . "000263578100001" . "Increasing the Level of Abstraction in FPGA-based Designes"@en . "Increasing the Level of Abstraction in FPGA-based Designes" . "2008-09-08+02:00"^^ . . "978-1-4244-1961-6" . . "International Conference on Field Programmable Logic and Applications" . "Zvy\u0161ov\u00E1n\u00ED \u00FArovn\u011B abstrakce v n\u00E1vrz\u00EDch zalo\u017Een\u00FDch na FPGA"@cs . "371852" . "Bartosinski, Roman" . "Zvy\u0161ov\u00E1n\u00ED \u00FArovn\u011B abstrakce v n\u00E1vrz\u00EDch zalo\u017Een\u00FDch na FPGA"@cs . "Kadlec, Ji\u0159\u00ED" . . "4"^^ . "Increasing the Level of Abstraction in FPGA-based Designes" . "Tradi\u010Dn\u00ED n\u00E1vrhov\u00E9 techniky pro FPGA obvody jsou zalo\u017Een\u00E9 na jazyc\u00EDch popisuj\u00EDc\u00EDch dan\u00FD hardware a na funkcion\u00E1ln\u00ED a postplace-and-route simulaci. Tedy na ov\u011B\u0159ov\u00E1n\u00ED spr\u00E1vnosti n\u00E1vrhu, detekci chyb a jejich n\u00E1sledn\u00E9m odstran\u011Bn\u00ED. S rostouc\u00ED slo\u017Eitost\u00ED navrhovan\u00FDch syst\u00E9m\u016F je vhodn\u00E9 si uv\u00E9st takov\u00E9 n\u00E1vrhov\u00E9 p\u0159\u00EDstupy, kter\u00E9 zvy\u0161uj\u00ED \u00FArove\u0148 abstrakce a z\u00E1rove\u0148 zachov\u00E1vaj\u00ED efektivitu navrohovan\u00E9ho hardwaru. Tento \u010Dl\u00E1nek jednu takovou n\u00E1vrhovou metodu p\u0159edstavuje. Je zalo\u017Eena na v\u00FDzkumu zab\u00FDvaj\u00EDc\u00EDm se v\u00EDce vl\u00E1knov\u00FDmi v\u00FDpo\u010Dty, zapouzd\u0159en\u00EDm a skl\u00E1datelnosti objekt\u016F, \u010D\u00E1ste\u010Dn\u00E9 dynamick\u00E9 rekonfiguraci a samo adaptaci. Metodologie je zalo\u017Eena na, v sou\u010Dasn\u00E9 dob\u011B, dostupn\u00FDch n\u00E1stroj\u00EDch pro n\u00E1vrhy v FPGA obvodech. Efektivita, touto metodou navr\u017Een\u00E9ho hardwaru, je dolo\u017Eena pomoc\u00ED z\u00E1kladn\u00EDch vektorov\u00FDch a maticov\u00FDch operac\u00ED."@cs . "4"^^ . "Z(AV0Z10750506)" . . . "Traditional design techniques for FPGAs are based on using hardware description languages, with functional and postplace-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. This paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. The methodology is based on currently available FPGA design tools. The efficiency of the methodology is evaluated on basic vector and matrix operations." . . "FPGA; dataflow; floating-point"@en .