"RIV/67985556:_____/06:00041103!RIV07-AV0-67985556" . "DSP; adaptive filter; logarithmic arithmetic; FPGA"@en . . . "Gregg, D." . "P(1M0567), Z(AV0Z10750506)" . . "Springer-Verlag" . . "2"^^ . "3"^^ . . . "[18F70F902857]" . . "Reconfigurable Computing: Architecures and Applications. Proceedings of the Second International Workshop ARC" . . "Tich\u00FD, Milan" . . "Efektivn\u00ED implementace (N)LMS filtr\u016F s vysok\u00FDm \u0159\u00E1dem v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce na FPGA"@cs . "473420" . "Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA"@en . "6"^^ . . "Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA"@en . . "Delft" . "Adaptivn\u00ED filtry se pou\u017E\u00EDvaj\u00ED v mnoha oblastech \u010D\u00EDslicov\u00E9ho zpracov\u00E1n\u00ED sign\u00E1l\u016F. \u010Cl\u00E1nek se zab\u00FDv\u00E1 implementac\u00ED LMS a NLMS algoritm\u016F v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce s pou\u017Eit\u00EDm FPGA. P\u0159edstavuje optimalizovan\u00E1 hardwarov\u00E1 makra pro oba algoritmy, vyu\u017E\u00EDvaj\u00EDc\u00ED logaritmickou aritmetiku. Makra jsou schopna pracovat na taktovac\u00ED frekvenci 80 MHz na \u010Dipu Xilinx XC2V1000-4, co\u017E p\u0159edstavuje v\u00FDkon 295 MFLOPS. Lze je pou\u017E\u00EDt k implementaci filtr\u016F \u0159\u00E1du 20 a\u017E 1022 pracuj\u00EDc\u00EDch se vzorkovac\u00ED frekvenc\u00ED p\u0159esahuj\u00EDc\u00ED 70 kHz."@cs . . "Efektivn\u00ED implementace (N)LMS filtr\u016F s vysok\u00FDm \u0159\u00E1dem v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce na FPGA"@cs . "Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA" . . "Schier, Jan" . "Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA" . "3-540-36708-X" . "311;316" . "2006-03-01+01:00"^^ . "Adaptive filters are used in many applications of digital signal processing. This paper deals with floating-point-like implementation of LMS and NLMS algorithms using FPGA hardware. We present an optimized cores for both algorithms, built using logarithmic arithmetic. The cores can be clocked at more than 80 MHz on the Xilinx XC2V1000-4 FPGA performing 295 MFLOPS. They can be used to implement adaptive filters of orders 20 to 1022 with a sampling rate exceeding 70 kHz." . . . . . "RIV/67985556:_____/06:00041103" . . "Berlin" . . . "Adaptive filters are used in many applications of digital signal processing. This paper deals with floating-point-like implementation of LMS and NLMS algorithms using FPGA hardware. We present an optimized cores for both algorithms, built using logarithmic arithmetic. The cores can be clocked at more than 80 MHz on the Xilinx XC2V1000-4 FPGA performing 295 MFLOPS. They can be used to implement adaptive filters of orders 20 to 1022 with a sampling rate exceeding 70 kHz."@en .