"\u010C\u00E1ste\u010Dn\u00E1 dynamick\u00E1 rekonfigurace umo\u017E\u0148uje zvy\u0161ovat funk\u010Dn\u00ED hustotu n\u00E1vrhu, co\u017E ale vede ke slo\u017Eit\u011Bj\u0161\u00EDm metod\u00E1m n\u00E1vrhu. Tento \u010Dl\u00E1nek popisuje metodologii a n\u00E1vrhov\u00FD postup pro rekonfigurovateln\u00E1 zapojen\u00ED z oblasti zpracov\u00E1n\u00ED sign\u00E1l\u016F a \u0159\u00EDd\u00EDc\u00ED techniky. Popisovan\u00FD postup za\u010D\u00EDn\u00E1 popisem v prost\u0159ed\u00ED Matlab/Simulink, kter\u00FD je p\u0159eveden do Handel-C a pak p\u0159elo\u017Een do VHDL a EDIFu a konfigura\u010Dn\u00ED informace pro FPGA obvody. Postup je p\u0159edveden na p\u0159\u00EDkladech."@cs . . . "P(GA102/04/2137), Z(AV0Z10750506)" . . . "\u010Cesk\u00E9 vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Praze" . "RIV/67985556:_____/06:00040204!RIV07-AV0-67985556" . . . "1-4244-0184-4" . "[61402075F797]" . . . . "2"^^ . "This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description an Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targetting the Atmel AT94K FPSLIC device." . . "FPGA; dynamic reconfiguration; FPSLIC; floating-point IP cores; design flow"@en . "Design and verification methodology for reconfigurable designs in Atmel FPSLIC"@en . "Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems" . . "RIV/67985556:_____/06:00040204" . . "Design and verification methodology for reconfigurable designs in Atmel FPSLIC" . "2"^^ . "This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description an Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating-point IP cores targetting the Atmel AT94K FPSLIC device."@en . "Metody n\u00E1vrhu a verifikace pro rekonfigurovateln\u00E9 n\u00E1vrhy v obvodu Atmel FPSLIC"@cs . "Design and verification methodology for reconfigurable designs in Atmel FPSLIC"@en . "470914" . . "Design and verification methodology for reconfigurable designs in Atmel FPSLIC" . . "Prague" . "Prague" . . . "2"^^ . . "79;80" . "Dan\u011Bk, Martin" . "Metody n\u00E1vrhu a verifikace pro rekonfigurovateln\u00E9 n\u00E1vrhy v obvodu Atmel FPSLIC"@cs . "2006-04-18+02:00"^^ . . . . "Kadlec, Ji\u0159\u00ED" . .