. "RIV/67985556:_____/05:00026140" . "Vysok\u00E1 \u0161kola chemicko-technologick\u00E1 v Praze" . "1;4" . "Technical Computing Prague 2005. 13th Annual Conference Proceeding" . "Beran, V." . "Reconfigurable image processing architecture with simulink prototyping support"@en . . "Schier, Jan" . . . . . "Zem\u010D\u00EDk, P." . . "Herout, A." . "A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip with a digital signal processor. Both these devices have characteristic that complement well each other for broad-class of data-intensive image-and video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. The paper describes both the HW and SW architecture of the system." . . "RIV/67985556:_____/05:00026140!RIV06-AV0-67985556" . . "[382F75B6BF8F]" . "540330" . "80-7080-577-3" . "A novel concept of an embedded image processing architecture is presented in the paper. This architecture is based on an interconnection of a programmable logical chip with a digital signal processor. Both these devices have characteristic that complement well each other for broad-class of data-intensive image-and video-processing tasks. For efficient utilization of such device, a multi-level configuration system is needed. The paper describes both the HW and SW architecture of the system."@en . "\u010Cl\u00E1nek pojedn\u00E1v\u00E1 o inovativn\u00ED architektu\u0159e pro zpracov\u00E1n\u00ED obrazu, zalo\u017Een\u00E9 na propojen\u00ED programovateln\u00E9ho logick\u00E9ho obvodu se dign\u00E1lov\u00FDm procesorem. Ob\u011B tato za\u0159\u00EDzen\u00ED se vz\u00E1jemn\u011B dopl\u0148uj\u00ED sv\u00FDmi charakteristikami, a jejich kombinace je v\u00FDhodn\u00E1 pro \u0159adu datov\u011B intenzivn\u00EDch \u00FAloh zpracov\u00E1n\u00ED obrazu a videa. Pro efektivn\u00ED vyu\u017Eit\u00ED takov\u00E9hoto za\u0159\u00EDzen\u00ED je t\u0159eba vyvinout v\u00EDce\u00FArov\u0148ov\u00FD konfigura\u010Dn\u00ED syst\u00E9m. V \u010Dl\u00E1nku je pops\u00E1na jak jeho hardwarov\u00E1, tak softwarov\u00E1 architektura."@cs . . "2005-11-15+01:00"^^ . "Reconfigurable image processing architecture with simulink prototyping support" . "4"^^ . "Praha" . "5"^^ . "Praha" . . . "Rekonfigurovateln\u00E1 architektura pro zpracov\u00E1n\u00ED obrazu s podporou rychl\u00E9ho modelov\u00E1n\u00ED v Simulinku"@cs . "Reconfigurable image processing architecture with simulink prototyping support" . . . . "P(1ET400750408), Z(AV0Z10750506)" . . "Rekonfigurovateln\u00E1 architektura pro zpracov\u00E1n\u00ED obrazu s podporou rychl\u00E9ho modelov\u00E1n\u00ED v Simulinku"@cs . . . "2"^^ . "Kov\u00E1\u0159, Bohumil" . "Reconfigurable image processing architecture with simulink prototyping support"@en . "embedded image processing; FPGA; DSP"@en . .