"3-540-22989-2" . . "2"^^ . "Springer-Verlag" . "He\u0159m\u00E1nek, Anton\u00EDn" . . "Berlin" . "Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA" . "2"^^ . . "In this paper, an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library is outlined. An advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations." . "Pou\u017Eit\u00ED logaritmick\u00E9 aritmetiky pro implementaci v\u00FDpo\u010Dtu rekurzivn\u00EDch nejmen\u0161\u00EDch \u010Dtverc\u016F v FPGA obvodu"@cs . . "Antverp" . . "3"^^ . . "RIV/67985556:_____/04:00106326" . "In this paper, an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library is outlined. An advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations."@en . "591742" . "[4D5981CC63EB]" . . "1149;1151" . "2004-08-30+02:00"^^ . "Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA"@en . . . "RIV/67985556:_____/04:00106326!RIV/2005/MSM/A16005/N" . "V \u010Dl\u00E1nku je pops\u00E1na FPGA implementace algoritmu pro QR aktualizaci pomoc\u00ED Givensov\u00FDch rotac\u00ED s pou\u017Eit\u00EDm High Speed Logarithmic Arithmetic (HSLA) aritmetick\u00E9 knihovny. V\u00FDhodou tohoto zp\u016Fsobu implementace je mal\u00E1 latence v\u00FDpo\u010Dtu a dostate\u010Dn\u00E1 p\u0159esnost operac\u00ED (srovnateln\u00E1 s v\u00FDpo\u010Dty v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce s jednoduchou p\u0159esnost\u00ED)"@cs . "Pou\u017Eit\u00ED logaritmick\u00E9 aritmetiky pro implementaci v\u00FDpo\u010Dtu rekurzivn\u00EDch nejmen\u0161\u00EDch \u010Dtverc\u016F v FPGA obvodu"@cs . . . . . "P(1ET300750402), P(1ET400750408), P(LN00B096), Z(AV0Z1075907)" . . "Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings" . "QR update;FPGA;logarithmic arithmetic"@en . . . . . "Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA" . . "Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA"@en . . "Schier, Jan" . .