. "blind equalization;CMA, FPGA;logarithmic arithmetic"@en . . . . "Architecture design for FPGA implementation of finite interval CMA" . "3"^^ . . . "1;4" . "Regalia, P." . . "2"^^ . "University of Technology" . "In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized." . . "N\u00E1vrh architektury pro FPGA implementaci blokov\u00E9ho CMA algoritmu (Finite interval CMA)"@cs . "Vienna" . . "Vienna" . . "In the paper, we present the architecture design of the Finite Interval Constant Modulus Algorithm (FI-CMA) for FPGA implementation. For floating point calculations required in the algorithm we use the library based on the Logarithmic Number System (LNS). In the design, the resource reuse and minimization of the total latency is emphasized."@en . . "N\u00E1vrh architektury pro FPGA implementaci blokov\u00E9ho CMA algoritmu (Finite interval CMA)"@cs . "Schier, Jan" . "Architecture design for FPGA implementation of finite interval CMA"@en . . . "4"^^ . "Architecture design for FPGA implementation of finite interval CMA"@en . . "[7246FBEF7DEA]" . . . . "V \u010Dl\u00E1nku je prezentov\u00E1n n\u00E1vrh architektury pro FPGA implementaci blokov\u00E9ho CMA algoritmu. Pro v\u00FDpo\u010Dty v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce, po\u017Eadovan\u00E9 v tomto algoritmu, byla pou\u017Eita aritmetick\u00E1 knihovna vyu\u017E\u00EDvaj\u00EDc\u00ED logaritmickou \u010D\u00EDselnou soustavu. N\u00E1vrh architektury je optimalizov\u00E1n pro v\u00EDcen\u00E1sobn\u00E9 vyu\u017Eit\u00ED HW prost\u0159edk\u016F a minimalizaci celkov\u00E9 latence"@cs . "P(1ET300750402), P(1ET400750408), P(LN00B096), Z(AV0Z1075907)" . "RIV/67985556:_____/04:00106325!RIV/2005/MSM/A16005/N" . . . "RIV/67985556:_____/04:00106325" . "555322" . "Proceedings of the 12th European Signal Processing Conference" . "3-200-00165-8" . . "2004-09-06+02:00"^^ . . . "He\u0159m\u00E1nek, Anton\u00EDn" . "Architecture design for FPGA implementation of finite interval CMA" .