"The paper describes in detail an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library. This library is based on integer computations with logarithmic equivalents of the floating-point numbers. An important advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations." . "FPGA implementation of recursive QR update using LNS arithmetic"@en . . "Delft" . "FPGA implementation of recursive QR update using LNS arithmetic" . . . "564797" . . "He\u0159m\u00E1nek, Anton\u00EDn" . "Hilvarenbeek" . "The paper describes in detail an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library. This library is based on integer computations with logarithmic equivalents of the floating-point numbers. An important advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations."@en . "Schier, Jan" . "\u010Cl\u00E1nek p\u0159in\u00E1\u0161\u00ED detailn\u00ED popis FPGA implementace algoritmu pro QR aktualizaci pomoc\u00ED Givensov\u00FDch rotac\u00ED s pou\u017Eit\u00EDm knihovny High Speed Logarithmic Arithmetic (HSLA). Tato knihovna vyu\u017E\u00EDv\u00E1 celo\u010D\u00EDseln\u00FDch v\u00FDpo\u010Dt\u016F na logaritm\u00FDch ekvivalentech \u010D\u00EDsel v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce. V\u00FDhodou tohoto p\u0159\u00EDstupu je mal\u00E1 latence v\u00FDpo\u010Dt\u016F a p\u0159esnost aritmetick\u00FDch operac\u00ED (srovnateln\u00E1 s v\u00FDpo\u010Dty v plovouc\u00ED \u0159\u00E1dov\u00E9 \u010D\u00E1rce s jednoduchou p\u0159esnost\u00ED)"@cs . "FPGA implementace rekurzivn\u00ED QR aktualizace s pou\u017Eit\u00EDm LNS aritmetiky"@cs . . . . "FPGA implementation of recursive QR update using LNS arithmetic"@en . "FPGA implementace rekurzivn\u00ED QR aktualizace s pou\u017Eit\u00EDm LNS aritmetiky"@cs . . "[9CEAC9857711]" . . . . "2"^^ . "FPGA implementation of recursive QR update using LNS arithmetic" . "Proceedings of the 4th IEEE Benelux Signal Processing Symposium" . "Technical University" . . "4"^^ . . . "RIV/67985556:_____/04:00106232" . "2"^^ . "givens rotations;FPGA;logarithmic arithmetic"@en . "P(LN00B096), Z(AV0Z1075907)" . . . . "1;4" . . "RIV/67985556:_____/04:00106232!RIV/2005/MSM/A16005/N" . . "2004-04-15+02:00"^^ .