. "8"^^ . "Integrated iterative approach to FPGA placement."@en . "Brno" . . "1"^^ . "RIV/67985556:_____/03:16030183!RIV/2004/AV0/A16004/N" . "80-214-2471-0" . . "[B197F1FB7FF8]" . "2003-09-24+02:00"^^ . "610703" . . "0"^^ . "This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders."@en . "1"^^ . "0"^^ . "Z(AV0Z1075907)" . "Vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Brn\u011B" . . "Po\u010D\u00EDta\u010Dov\u00E9 Architektury & Diagnostika PAD 2003." . . "This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders." . . . "RIV/67985556:_____/03:16030183" . . "FPGA placement; global routing; integrated approach"@en . "Zv\u00EDkovsk\u00E9 Podhrad\u00ED [CZ]" . . "Integrated iterative approach to FPGA placement." . "Integrated iterative approach to FPGA placement."@en . . . . . "43;50" . "Integrated iterative approach to FPGA placement." . "Dan\u011Bk, Martin" . . .