. . "10439" . . . . . "IEEE Computer Society" . "3"^^ . . "Pu\u0161, Viktor" . "[FF747A4223DA]" . "3"^^ . . . "Ko\u0159enek, Jan" . "Design Methodology of Configurable High Performance Packet Parser for FPGA" . "2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)" . . "Warsaw, Poland" . "Warsaw, Poland" . "FPGA; Latency; Packet Parsing"@en . . . "000346734200038" . "978-1-4799-4558-0" . . . "Design Methodology of Configurable High Performance Packet Parser for FPGA"@en . "Design Methodology of Configurable High Performance Packet Parser for FPGA"@en . "2014-04-22+02:00"^^ . "P(ED1.1.00/02.0070), P(LM2010005), S" . . "6"^^ . "Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols."@en . . . "Design Methodology of Configurable High Performance Packet Parser for FPGA" . . "RIV/63839172:_____/14:10130332" . "RIV/63839172:_____/14:10130332!RIV15-MSM-63839172" . . . "Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. The parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols." . "Kekely, Luk\u00E1\u0161" . "2334-3133" .