"Syst\u00E9m pro detekci naru\u0161en\u00ED po\u010D\u00EDta\u010Dov\u00E9 s\u00EDt\u011B ur\u010Deny pro multigigabitov\u00E9 s\u00EDt\u011B"@cs . . "2007-01-01+01:00"^^ . "Z(MSM0021630528), Z(MSM6383917201)" . . "Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on Field-Programmable Gate Array (FPGA). Core generator for automatic mapping of IDS rules to FPGA logic was designed to assure fast packet classification and high speed pattern matching. Proposed architecture has been evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6X card theoretical throughput 6.4~Gbps was achieved for all Snort rules. The designed system can be configured by rules described in Snort format using web interface." . . . . . "RIV/63839172:_____/07:00000640!RIV08-MSM-63839172" . . "Syst\u00E9m pro detekci naru\u0161en\u00ED po\u010D\u00EDta\u010Dov\u00E9 s\u00EDt\u011B ur\u010Deny pro multigigabitov\u00E9 s\u00EDt\u011B"@cs . . . . "427399" . "[EC26F50F474A]" . "Krakow, Poland" . "2"^^ . "Krakow, Poland" . "361;364" . "2"^^ . "Kobiersk\u00FD, Petr" . "\u010Cl\u00E1nek popisuje architekturu sondy Traffic Scanner, kter\u00E9 slou\u017E\u00ED pro detekci podez\u0159el\u00E9ho provozu na s\u00EDti."@cs . . "1-4244-1161-0" . . "Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007)" . "Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on Field-Programmable Gate Array (FPGA). Core generator for automatic mapping of IDS rules to FPGA logic was designed to assure fast packet classification and high speed pattern matching. Proposed architecture has been evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6X card theoretical throughput 6.4~Gbps was achieved for all Snort rules. The designed system can be configured by rules described in Snort format using web interface."@en . . . . "RIV/63839172:_____/07:00000640" . . . "4"^^ . "IEEE Computer Society" . "Intrusion Detection System Intended for Multigigabit Networks" . "Intrusion Detection System Intended for Multigigabit Networks" . "Traffic Scanner; Snort; IDS; pattern matching"@en . . "Ko\u0159enek, Jan" . "Intrusion Detection System Intended for Multigigabit Networks"@en . . "Intrusion Detection System Intended for Multigigabit Networks"@en .