. . . "1"^^ . "S" . "RIV/49777513:23220/14:43923741" . "1"^^ . . "45799" . "Softwarov\u00E1 implementace koherentn\u00EDho QPSK p\u0159ij\u00EDma\u010De ve VHDL pro synt\u00E9zu na FPGA" . . "Software implementation of coherent QPSK receiver in VHDL for FPGA synthesis"@en . "RIV/49777513:23220/14:43923741!RIV15-MSM-23220___" . . . . . . . "Implentation of coherent software defined QPSK receiver in VHDL language is intended for synthesis on FPGA and contains following components. It involves matched FIR filter, symbol synchronization block and carrier phase rotation block. Implementation was carried out on the development kit with Altera Cyclone IV FPGA supplemented with expansion board that contains fast AD / DA converters. It is possible to sample the intermediate frequency (tested Fcent=4.57MHz) or baseband. This property depends on the RF frontend. Matched filter is designed as a fully parallel, pipelined processing is used. Symbol synchronization section based on PLL contains Farrow structure FIR interpolator. This structure can be very efficiently implemented on gate array. Error detector works with two samples per symbol and is based on zero crossing detection. Carrier phase rotation block includes a numerically controlled oscillator and calculation of trigonometric functions is implemented with the CORDIC algorithm. The proposal is designed as strictly modular; the SDR receiver can be easily modified and adapted for specific applications. Matlab simulation has been done for all blocks and following RTL simulation with HDL test bench in Modelsim."@en . "v\u00FDsledek je vyu\u017E\u00EDv\u00E1n p\u0159\u00EDjemcem Z\u010CU, ekonomick\u00E9 parametry se neuv\u00E1d\u011Bj\u00ED" . . "Softwarov\u00E1 implementace koherentn\u00EDho QPSK p\u0159ij\u00EDma\u010De ve VHDL pro synt\u00E9zu na FPGA"@cs . "Fiala, Pavel" . "[49DC5817ABAD]" . "Software implementation of coherent QPSK receiver in VHDL for FPGA synthesis"@en . "Kontakt: ing. Pavel Fiala, Univerzitn\u00ED 8, 306 14 Plze\u0148, 377634267" . . "VHDL; synchronization; SDR; RF; receiver; FIR filter; FPGA; CORDIC"@en . "Implementace koherentn\u00EDho softwarov\u011B definovan\u00E9ho QPSK p\u0159ij\u00EDma\u010De v jazyce VHDL je ur\u010Dena pro synt\u00E9zu na hradlov\u00E9m poli FPGA a obsahuje d\u00E1le uveden\u00E9 komponenty. Jedn\u00E1 se o p\u0159izp\u016Fsobeny FIR filtr, blok symbolov\u00E9 synchronizace a blok pro synchronizaci (obnovu) nosn\u00E9 vlny. Implementace byla provedena na v\u00FDvojov\u00E9m kitu s Altera Cyclone IV FPGA dopln\u011Bn\u00E9m o roz\u0161i\u0159uj\u00EDc\u00ED kartou, kter\u00E1 obsahuje rychl\u00E9 AD/DA p\u0159evodn\u00EDky. Je mo\u017En\u00E9 dle pot\u0159eby vzorkovat sign\u00E1l na mezifrekven\u010Dn\u00EDm kmito\u010Dtu (testovan\u00E1 Fcent=4.57MHz) nebo v z\u00E1kladn\u00EDm p\u00E1smu. Tato vlastnost z\u00E1vis\u00ED na pou\u017Eit\u00E9 RF \u010D\u00E1sti. P\u0159izp\u016Fsoben\u00FD filtr je \u0159e\u0161en jako pln\u011B paraleln\u00ED, je vyu\u017Eito z\u0159et\u011Bzen\u00E9ho zpracov\u00E1n\u00ED. Blok symbolov\u00E9 synchronizace zalo\u017Een\u00FD na f\u00E1zov\u00E9m z\u00E1v\u011Bsu obsahuje interpol\u00E1tor \u0159e\u0161en\u00FD jako FIR filtr s tzv. Farrow strukturou, kterou lze velice efektivn\u011B implementovat na hradlov\u00E9m poli. Chybov\u00FD detektor pracuje se 2 vzorky na symbol a je zalo\u017Een na detekci pr\u016Fchodu nulou. Blok synchronizace nosn\u00E9 vlny obsahuje numericky kontrolovan\u00FD oscil\u00E1tor a pro v\u00FDpo\u010Det goniometrick\u00FDch funkc\u00ED je vyu\u017Eito algoritmu CORDIC. N\u00E1vrh je \u0159e\u0161en jako ryze modul\u00E1rn\u00ED, parametry tohoto SDR p\u0159ij\u00EDma\u010De lze snadno modifikovat a p\u0159izp\u016Fsobit konkr\u00E9tn\u00ED aplikaci. Pro v\u0161echny bloky byla provedena simulace v programu Matlab a n\u00E1sledn\u011B RTL simulace v programu Modelsim."@cs . . . . "22110-SW004-2014" . "Implementace koherentn\u00EDho softwarov\u011B definovan\u00E9ho QPSK p\u0159ij\u00EDma\u010De v jazyce VHDL je ur\u010Dena pro synt\u00E9zu na hradlov\u00E9m poli FPGA a obsahuje d\u00E1le uveden\u00E9 komponenty. Jedn\u00E1 se o p\u0159izp\u016Fsobeny FIR filtr, blok symbolov\u00E9 synchronizace a blok pro synchronizaci (obnovu) nosn\u00E9 vlny. Implementace byla provedena na v\u00FDvojov\u00E9m kitu s Altera Cyclone IV FPGA dopln\u011Bn\u00E9m o roz\u0161i\u0159uj\u00EDc\u00ED kartou, kter\u00E1 obsahuje rychl\u00E9 AD/DA p\u0159evodn\u00EDky. Je mo\u017En\u00E9 dle pot\u0159eby vzorkovat sign\u00E1l na mezifrekven\u010Dn\u00EDm kmito\u010Dtu (testovan\u00E1 Fcent=4.57MHz) nebo v z\u00E1kladn\u00EDm p\u00E1smu. Tato vlastnost z\u00E1vis\u00ED na pou\u017Eit\u00E9 RF \u010D\u00E1sti. P\u0159izp\u016Fsoben\u00FD filtr je \u0159e\u0161en jako pln\u011B paraleln\u00ED, je vyu\u017Eito z\u0159et\u011Bzen\u00E9ho zpracov\u00E1n\u00ED. Blok symbolov\u00E9 synchronizace zalo\u017Een\u00FD na f\u00E1zov\u00E9m z\u00E1v\u011Bsu obsahuje interpol\u00E1tor \u0159e\u0161en\u00FD jako FIR filtr s tzv. Farrow strukturou, kterou lze velice efektivn\u011B implementovat na hradlov\u00E9m poli. Chybov\u00FD detektor pracuje se 2 vzorky na symbol a je zalo\u017Een na detekci pr\u016Fchodu nulou. Blok synchronizace nosn\u00E9 vlny obsahuje numericky kontrolovan\u00FD oscil\u00E1tor a pro v\u00FDpo\u010Det goniometrick\u00FDch funkc\u00ED je vyu\u017Eito algoritmu CORDIC. N\u00E1vrh je \u0159e\u0161en jako ryze modul\u00E1rn\u00ED, parametry tohoto SDR p\u0159ij\u00EDma\u010De lze snadno modifikovat a p\u0159izp\u016Fsobit konkr\u00E9tn\u00ED aplikaci. Pro v\u0161echny bloky byla provedena simulace v programu Matlab a n\u00E1sledn\u011B RTL simulace v programu Modelsim." . . "http://partnerstvi.fel.zcu.cz/vysledky" . . . "23220" . "Softwarov\u00E1 implementace koherentn\u00EDho QPSK p\u0159ij\u00EDma\u010De ve VHDL pro synt\u00E9zu na FPGA" . . . . "Softwarov\u00E1 implementace koherentn\u00EDho QPSK p\u0159ij\u00EDma\u010De ve VHDL pro synt\u00E9zu na FPGA"@cs .