. . "V\u00FDsledek je vyu\u017E\u00EDv\u00E1n p\u0159\u00EDjemcem, ekonomick\u00E9 parametry se neuv\u00E1d\u00ED." . . "Jedn\u00E1 se o software implementovan\u00FD do programovateln\u00E9ho logick\u00E9ho pole FPGA. Tento software byl navr\u017Een pro specifick\u00E9 po\u017Eadavky \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F."@cs . "Universal block modulator for control of multilevel converters implemented in the FPGA"@en . . . "2"^^ . . "Modulator, Multilevel convertor"@en . "RIV/49777513:23220/13:43919271!RIV14-TA0-23220___" . "23220" . "V\u00FDsledek vyvinut, testov\u00E1n a vyu\u017E\u00EDv\u00E1n p\u0159\u00EDjemcem." . "This software is developed for field programmable gate array FPGA. This software has been designed for the specific requirements of multilevel convertors control."@en . . "2"^^ . . . "[DED6FFFC1269]" . "http://partnerstvi.fel.zcu.cz/vysledky" . . . "Jan\u00EDk, Du\u0161an" . . "Ko\u0161an, Tom\u00E1\u0161" . . "Univerz\u00E1ln\u00ED blokov\u00FD modul\u00E1tor pro \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F implementovan\u00FD v obvodu FPGA"@cs . "P(TA01010863), S" . . "Univerz\u00E1ln\u00ED blokov\u00FD modul\u00E1tor pro \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F implementovan\u00FD v obvodu FPGA"@cs . "RIV/49777513:23220/13:43919271" . "Univerz\u00E1ln\u00ED blokov\u00FD modul\u00E1tor pro \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F implementovan\u00FD v obvodu FPGA" . . . . "Jedn\u00E1 se o software implementovan\u00FD do programovateln\u00E9ho logick\u00E9ho pole FPGA. Tento software byl navr\u017Een pro specifick\u00E9 po\u017Eadavky \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F." . "22190-SW002-2013" . "Universal block modulator for control of multilevel converters implemented in the FPGA"@en . . "112656" . . "Univerz\u00E1ln\u00ED blokov\u00FD modul\u00E1tor pro \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F implementovan\u00FD v obvodu FPGA" .