"N\u00EDzko\u00FArov\u0148ov\u00FD kontrol\u00E9r pro t\u0159\u00ED\u00FArov\u0148ov\u00FD NPC/ANPC m\u011Bni\u010D implementovan\u00FD v CPLD" . "N\u00EDzko\u00FArov\u0148ov\u00FD kontrol\u00E9r pro t\u0159\u00ED\u00FArov\u0148ov\u00FD NPC/ANPC m\u011Bni\u010D implementovan\u00FD v CPLD"@cs . "RIV/49777513:23220/12:43916610" . "N\u00EDzko\u00FArov\u0148ov\u00FD kontrol\u00E9r pro t\u0159\u00ED\u00FArov\u0148ov\u00FD NPC/ANPC m\u011Bni\u010D implementovan\u00FD v CPLD" . . . "23220" . . "RIV/49777513:23220/12:43916610!RIV13-MSM-23220___" . "154280" . "Tato pr\u00E1ce se zab\u00FDv\u00E1 problematikou n\u00EDzko\u00FArov\u0148ov\u00E9ho \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F. Budeme se zab\u00FDvat implementac\u00ED nov\u00E9ho kontrol\u00E9ru pro v\u00EDce \u00FArov\u0148ov\u00E9 budi\u010De. Za\u0159\u00EDzen\u00ED obsahuje jeden obvod typu CPLD, kter\u00FD \u0159\u00EDd\u00ED sp\u00EDn\u00E1n\u00ED v\u00FDkonov\u00FDch IGBT p\u0159es opticky odd\u011Blen\u00E9 v\u00FDkonov\u00E9 budi\u010De. Hlavn\u00ED v\u00FDhodou pou\u017Eit\u00E9ho \u0159e\u0161en\u00ED je redukce po\u010Dtu \u0159\u00EDd\u00EDc\u00EDch sign\u00E1l\u016F z procesoru. Jsou pot\u0159eba jen t\u0159i synchronn\u00ED PWM sign\u00E1ly a jeden hlavn\u00ED \u0159\u00EDd\u00EDc\u00ED sign\u00E1l ENABLE pro \u0159\u00EDzen\u00ED \u0161esti IGBT." . "N\u00EDzko\u00FArov\u0148ov\u00FD kontrol\u00E9r pro t\u0159\u00ED\u00FArov\u0148ov\u00FD NPC/ANPC m\u011Bni\u010D implementovan\u00FD v CPLD"@cs . . . . "Ko\u0161an, Tom\u00E1\u0161" . . "Low level controler for three-level NPC/ANPC converter implemented in CPLD"@en . "In this paper, we will discuss a new driver for multi-level converter. Device consists of one CPLD device, which controls each IGBT transistor through isolated power driver. Main advantage of this device lays in extending number of outputs according to number of inputs. Only three synchronous PWM inputs and one ENABLE input are required for driving six IGBT transistors in basic mode."@en . . "Low level controler for three-level NPC/ANPC converter implemented in CPLD"@en . . "P(ED2.1.00/03.0094), P(TA01010863)" . . . "Tato pr\u00E1ce se zab\u00FDv\u00E1 problematikou n\u00EDzko\u00FArov\u0148ov\u00E9ho \u0159\u00EDzen\u00ED v\u00EDce\u00FArov\u0148ov\u00FDch m\u011Bni\u010D\u016F. Budeme se zab\u00FDvat implementac\u00ED nov\u00E9ho kontrol\u00E9ru pro v\u00EDce \u00FArov\u0148ov\u00E9 budi\u010De. Za\u0159\u00EDzen\u00ED obsahuje jeden obvod typu CPLD, kter\u00FD \u0159\u00EDd\u00ED sp\u00EDn\u00E1n\u00ED v\u00FDkonov\u00FDch IGBT p\u0159es opticky odd\u011Blen\u00E9 v\u00FDkonov\u00E9 budi\u010De. Hlavn\u00ED v\u00FDhodou pou\u017Eit\u00E9ho \u0159e\u0161en\u00ED je redukce po\u010Dtu \u0159\u00EDd\u00EDc\u00EDch sign\u00E1l\u016F z procesoru. Jsou pot\u0159eba jen t\u0159i synchronn\u00ED PWM sign\u00E1ly a jeden hlavn\u00ED \u0159\u00EDd\u00EDc\u00ED sign\u00E1l ENABLE pro \u0159\u00EDzen\u00ED \u0161esti IGBT."@cs . . . "NPC, ANPC, CPLD"@en . . . "1"^^ . "[BF8C9E6460D7]" . "1"^^ . . .