. "23220" . . . "Algoritmus pro vy\u010D\u00EDslen\u00ED exponenci\u00E1ln\u00ED funkce navr\u017Een\u00FD pro programovateln\u00E9 logick\u00E9 obvody FPGA"@cs . "Algoritmus pro vy\u010D\u00EDslen\u00ED exponenci\u00E1ln\u00ED funkce navr\u017Een\u00FD pro programovateln\u00E9 logick\u00E9 obvody FPGA" . . . "shift-and-add algorithm; exponential function; FPGA"@en . "The paper deals with implementation of shift-and-add algorithm for calculation of exponential function in FPGA environment. First, the basic idea of algorithm is presented. Then, the algorithm architecture design for FPGA is discussed in detail. Finally, simulation results show the achieved exponential function computation accuracy."@en . "Tento \u010Dl\u00E1nek se zab\u00FDv\u00E1 implementac\u00ED algoritmu, kter\u00FD pro v\u00FDpo\u010Det vyu\u017E\u00EDv\u00E1 operace bitov\u00E9ho posuvu a sou\u010Dtu, pro v\u00FDpo\u010Det exponenci\u00E1ln\u00ED funkce v prost\u0159ed\u00ED FPGA. Nejd\u0159\u00EDve je p\u0159edstaven z\u00E1kladn\u00ED princip algoritmu. N\u00E1sleduje detailn\u00ED popis navr\u017Een\u00E9 architektury algoritmu pro FPGA. Na konci \u010Dl\u00E1nku jsou uvedeny z\u00EDskan\u00E9 v\u00FDsledky ze simulace."@cs . . . . "1"^^ . "RIV/49777513:23220/10:00503508!RIV11-MSM-23220___" . . "Algoritmus pro vy\u010D\u00EDslen\u00ED exponenci\u00E1ln\u00ED funkce navr\u017Een\u00FD pro programovateln\u00E9 logick\u00E9 obvody FPGA"@cs . "Algoritmus pro vy\u010D\u00EDslen\u00ED exponenci\u00E1ln\u00ED funkce navr\u017Een\u00FD pro programovateln\u00E9 logick\u00E9 obvody FPGA" . "Tento \u010Dl\u00E1nek se zab\u00FDv\u00E1 implementac\u00ED algoritmu, kter\u00FD pro v\u00FDpo\u010Det vyu\u017E\u00EDv\u00E1 operace bitov\u00E9ho posuvu a sou\u010Dtu, pro v\u00FDpo\u010Det exponenci\u00E1ln\u00ED funkce v prost\u0159ed\u00ED FPGA. Nejd\u0159\u00EDve je p\u0159edstaven z\u00E1kladn\u00ED princip algoritmu. N\u00E1sleduje detailn\u00ED popis navr\u017Een\u00E9 architektury algoritmu pro FPGA. Na konci \u010Dl\u00E1nku jsou uvedeny z\u00EDskan\u00E9 v\u00FDsledky ze simulace." . "1"^^ . . . "Algorithm for calculation of exponential function designed for programmable logic device FPGA"@en . . "S" . "Algorithm for calculation of exponential function designed for programmable logic device FPGA"@en . . "245936" . "RIV/49777513:23220/10:00503508" . . "[C33860183345]" . "Jan\u00EDk, Du\u0161an" .