. "This paper describes a new architecture of a digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other methods. Presented synthesizer is the most suitable for the design of VLSI a rchitectures or for programmable logical devices (CPLD, FPGA). This synthesizer has a disadvantage in low output frequency, which can be overcome by using this synthesizer together with phase-locked loop."@en . . . "Klusal, Milo\u0161" . . "This paper describes a new architecture of a digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other methods. Presented synthesizer is the most suitable for the design of VLSI a rchitectures or for programmable logical devices (CPLD, FPGA). This synthesizer has a disadvantage in low output frequency, which can be overcome by using this synthesizer together with phase-locked loop." . "205-207" . "80-7082-951-6" . . . . "FPGA realization of the digital frequency synthesizer"@en . "FPGA;digital frequency synthesizer;direct digital synthesis;phase-locked loop"@en . "607658" . "3"^^ . "FPGA realization of the digital frequency synthesizer" . "\u0160tork, Milan" . . "FPGA realization of the digital frequency synthesizer" . . "Applied Electronics 2003" . "Z\u00E1pado\u010Desk\u00E1 univerzita v Plzni" . "Pilsen" . . . "Z\u010CU FEL Plze\u0148" . "[94E88263A4AC]" . "23220" . . . "2"^^ . "RIV/49777513:23220/03:00000027!RIV/2004/MSM/232204/N" . . . "RIV/49777513:23220/03:00000027" . . . "0"^^ . . "P(LN00B084)" . "2003-09-10+02:00"^^ . "0"^^ . "FPGA realization of the digital frequency synthesizer"@en . "2"^^ .